Reorganized Autogen

vhdl folder has been renamed ipcore
quartus folder has been moved from the vhdl/ipcore folder to the root
directory of the repo
Files not directly related vhdl/ipcore folder have been moved to the
root

Matlab wrappers of Python functions have been removed

autogen_quartus no longer uses the DataplaneConfig class, instead it
uses WorkflowConfig which is essentially a cut down version that only
parses information used by the Quartus workflow. It does still use the same
configuration file though in practice.

All Python calls that currently have a command-line option are now
called from Autogen via a system call using that interface

Author: fe-wickham

vhdl/autogen.m renamed to autogen.m

@@ -2,7 +2,7 @@
 import sys
 import logging
 
-from dataplane_config import DataplaneConfig
+from quartus.workflow_config import WorkflowConfig
 from quartus.quartus_workflow import execute_quartus_workflow
 
 
@@ -11,9 +11,9 @@ def main(inputFilename, working_dir, log_to_file=False):
         working_dir += "/"
     logger = init_logging(logging.INFO, log_to_file)
     try:
-        dataplane_config = DataplaneConfig.parse_json(inputFilename)
+        config = WorkflowConfig.parse_json(inputFilename)
         execute_quartus_workflow(
-            dataplane_config.target_system, dataplane_config.custom_components, dataplane_config.clock_rate, working_dir)
+            config.target_system, config.custom_components, config.clock_rate, working_dir)
     finally:
         logger.info("exit")
 

vhdl/autogen_quartus.py renamed to autogen_quartus.py

@@ -266,14 +266,14 @@ def parseargs():
     """
     parser = argparse.ArgumentParser(
         description="Generates a Platform Design/Qsys component as _hw.tcl file")
-    parser.add_argument('-j', '--json',
+    parser.add_argument('-c', '--config',
                         help="JSON file containing autogen configuration")
     parser.add_argument('-w', '--working-dir',
-                        help="Working directory to generate the Platform Design/Qsys component in")
+                        help="Working directory to generate the Platform Designer component in")
     parser.add_argument('-o', '--output-filename',
                         help="Name of the output file, recommended to end in '_hw.tcl'")
     args = parser.parse_args()
-    return (args.json, args.output_filename, args.working_dir)
+    return (args.config, args.output_filename, args.working_dir)
 
 
 if __name__ == "__main__":

device_drivers/genDeviceDriver.m

@@ -33,7 +33,7 @@ def __init__(self):
 
         self.compatible_flag = "Fill me in"
         self.group = "Fill me in"
-        self.vendor = "fe"
+        self.vendor = "al"
         self.target_system = ""
 
         self.clock_rate = 0

device_drivers/genMakefile.m

@@ -373,15 +373,15 @@ def convert_default_value(value, datatype):
 def parseargs():
     parser = argparse.ArgumentParser(description=\
         "Generate VHDL code for Avalon streaming and memory-mapped interfaces.")
-    parser.add_argument('infile',
+    parser.add_argument('-c','--config_file',
         help="json file containing the interface and register specifications")
     parser.add_argument('-v', '--verbose', action='store_true',
         help="verbose output")
     parser.add_argument('-p', '--print', action='store_true', dest='print_output',
         help="print out the generated vhdl code")
-    parser.add_argument('outfile', help="the name of the output vhdl file")
+    parser.add_argument('-o', '--outfile', help="the name of the output vhdl file")
     args = parser.parse_args()
-    return (args.infile, args.outfile, args.verbose, args.print_output)
+    return (args.config_file, args.outfile, args.verbose, args.print_output)
 
 
 # TODO: make a default filename?

vhdl/__init__.py renamed to ipcore/__init__.py

@@ -0,0 +1,24 @@
+import json
+import math
+import os
+
+class WorkflowConfig:
+    def __init__(self):
+        self.custom_components = []
+        self.target_system = ""
+        self.clock_rate = 0
+        self.working_dir = ""
+
+    
+    @staticmethod
+    def parse_json(inputFilename):
+        with open(inputFilename, "r") as file:
+            in_str = file.read()
+            json_dict = json.loads(in_str)
+            config = WorkflowConfig()
+           
+            config.clock_rate = json_dict.get('clocks') and json_dict.get('clocks')['system_frequency_Hz']
+            config.target_system = json_dict.get("target_system")
+            config.custom_components = json_dict.get("custom_components") or [json_dict.get('model_name')]
+            config.working_dir = json_dict.get("working_dir")
+        return config

vhdl/create_hw_tcl.py renamed to ipcore/create_hw_tcl.py

@@ -82,32 +82,30 @@
 
 %% Generate the Avalon VHDL wrapper for the VHDL code generated by the HDL Coder
 disp('vgen: Creating Avalon VDHL wrapper.')
-infile = [avalon.entity '.json'];
+config_file = [avalon.entity '.json'];
 outfile = [hdlpath filesep avalon.entity '_avalon.vhd'];
-vgenAvalonWrapper(infile, outfile, false, false);
+system("python " + mp.ipcore_codegen_path + filesep + "vgenAvalonWrapper.py -c " + config_file + " -o " + outfile);
 disp(['      created vhdl file: ' outfile])
 
 %% Generate the .tcl script to be used by Platform Designer in Quartus
 disp('vgen: Creating .tcl script for Platform Designer.')
-config_file = [avalon.entity '.json'];
 % NOTE: platform designer only adds components if they have the _hw.tcl suffix
 outfile = [hdlpath filesep avalon.entity '_avalon_hw.tcl'];
 disp(['file ' config_file ' out ' outfile ' path ' hdlpath])
-vgenHwTcl(config_file, outfile, hdlpath)
-
+system("python " + mp.ipcore_codegen_path + filesep + "create_hw_tcl.py -c " + config_file + " -w " + hdlpath + " -o " + outfile );
 disp(['      created tcl file: ' outfile])
 
 disp('vgen: Executing Quartus workflow')
 if ispc; second_cmd = "&"; else; second_cmd = ";"; end
 working_dir = hdlpath + "/quartus/";
-quartus_workflow_cmd = "python " + mp.vhdl_codegen_path + "/autogen_quartus.py -j " + config_file ...
+
+quartus_workflow_cmd = "python " + mp.codegen_path + "/autogen_quartus.py -j " + config_file ...
     + " -w " + working_dir + " -l " + second_cmd + " exit &";
-disp(quartus_workflow_cmd)
 system(quartus_workflow_cmd);
 
+% Stream the Quartus workflow log and display it to the user
 fid = fopen("autogen_quartus.log");
 if fid>0
-    % loop until end of file is reached
     while 1
         % read the current line
         where = ftell(fid);
@@ -122,22 +120,20 @@
             disp(line)
         end
     end
-    % close the file
     fclose(fid);
 end
 
-%disp("r: ---------------------------------------------------\n" + r)
 disp('Executed Quartus workflow')
 
 %% Generate the device driver code
 disp('Creating device driver.')
 outfile = [hdlpath filesep mp.model_name '.c'];
-genDeviceDriver(infile, outfile)
+py.JsonToDriver.JsonToDriver(config_file, outfile)
 disp(['      created device driver: ' outfile])
 
 %% Generate kernel module build files
 disp('Creating Makefile and Kbuild.')
-genMakefile([hdlpath filesep], mp.model_name)
+system("python " + mp.driver_codegen_path + filesep + "gen_makefile.py " + [hdlpath filesep] + " " + mp.model_name);
 disp(['      created Makefile: ' [hdlpath filesep 'Makefile']])
 disp(['      created Kbuild: ' [hdlpath filesep 'Kbuild']])
 
@@ -159,7 +155,6 @@
 end
 
 % TODO: this file now generates C code, but "vgen" make it seem like it is just VHDL still. This should be changed, and the repository should be reorganized a bit. 
-%       This file shouldn't live in the vhdl folder anymore.
 %% Build Device Tree blob
 project_revision = mp.model_name + "_" + mp.target_system;
 sopcinfo_file = hdlpath + "/quartus/" + mp.target_system + '_system.sopcinfo';