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Sapere aude.
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Sapere aude.

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franout/README.md

Hello world 👋

  • 🔭 I’m currently working (hard!) on my PhD in Computer Engineering @ Politecnico di Torino on "System-Level-Test techniques for Automotive SoCs"
  • M.Sc. in Embedded Systems Engineering @ Politecnico di Torino, Italy, A.Y. 2020.
  • Erasmus Student @ Chalmers University of Technology during A.Y. 2019/2020
  • 🌱 I’m currently learning.
  • 👯 I’m looking to collaborate on Real-Time Operating Systems

𝗠𝘆 𝗧𝗲𝗰𝗸 𝗦𝘁𝗮𝗰𝗸

Python C++ Shell AssemblyScript

Ansible Git GitLab GitHub

TCL - System Verilog - Verilog - VHDL

𝗦𝘁𝗮𝘁𝘀

franout's github stats

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  1. tensorflow_for_pynqz2 tensorflow_for_pynqz2 Public

    tensorflor 2.1 wheel for pynq z2 ( zynq 7000 xilinx SoC ), cross compiled with different compiler's flags using the script provided by tensorflow for building it for rasberry

    Shell 7

  2. DLX_project DLX_project Public

    Deluxe RISC processor

    VHDL 5

  3. Cogitantium Cogitantium Public

    Hardware Accelerator for ML

    VHDL 4 1

  4. CTH_HPC CTH_HPC Public

    High parallel computing @ Chalmers University of technology

    C

  5. Testing_and_fault_tolerance Testing_and_fault_tolerance Public

    Testing_fault_tolerance

    VHDL

  6. DPL_termometer DPL_termometer Public

    Implementation of a termometer

    C 1

177 contributions in the last year

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Activity overview

Loading A graph representing franout's contributions from February 18, 2024 to February 23, 2025. The contributions are 91% commits, 6% pull requests, 2% code review, 1% issues.

Contribution activity

February 2025

61 contributions in private repositories Feb 3 – Feb 22
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