All pull requests

Pull requests

• GF61 weakModM61 on AMD: take a >> 61 from two v_alignbit_b32 (not in the MIDDLE >= 16 middle kernels)

  #191·MarkRose opened Oct 28, 2026·

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• GF61 twiddle tables: store cmul's Karatsuba terms, read them on AMD

  #190·MarkRose opened Oct 28, 2026·

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• GF61: a cheaper mul64 for products with a + b < 2^64

  #189·MarkRose opened Oct 28, 2026·

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• timeStr: use localtime_r/gmtime_r so worker threads don't race on libc's shared struct tm

  #188·MarkRose opened Oct 28, 2026·

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• Unroll the GF31 twiddle loops in tailSquare's fft_HEIGHT

  #187·MarkRose opened Oct 28, 2026·

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• Split carryFused and the tail kernels into launches under 1 ms on gfx11/gfx12

  #186·MarkRose opened Oct 28, 2026·

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• L2_STRIPING fftMiddleInGF61: use zerohack so MIDDLE=16 does not spill

  #185·MarkRose opened Oct 28, 2026·

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• In-place PFA fftMiddleOut: rotate the rows in the store, not with selects

  #184·MarkRose opened Oct 28, 2026·

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• GF61 PFA middles at MIDDLE 10, 12, 14: unroll the column loops, fence the columns

  #183·MarkRose opened Oct 28, 2026·

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• In-place (INPLACE=1) fftMiddleInGF61: use zerohack at MIDDLE=16 on AMD (−3 to −11 % on 7900 XTX)

  #182·MarkRose opened Oct 27, 2026·

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• In-place fftMiddleInGF61: use zerohack at MIDDLE=16 too (−3 to −12 % with INPLACE=2 on 7900 XTX)

  #181·MarkRose opened Oct 27, 2026·

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• GF61 PFA 9/11/15 middles: no scratch (fixes the 1:512:9:512 slowdown from #158)

  #180·MarkRose opened Oct 27, 2026·

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• -tune 4k: optional group timing the non-favored 4K-wide shapes

  #179·MarkRose opened Oct 26, 2026·

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• -tune: time 256RADIX8_W/H (NTT −4.3 % at 1:256:8:256 on 7900 XTX)

  #178·MarkRose opened Oct 26, 2026·

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• -tune: sweep SHUFL_BYTES_W/H, HOIST_W/H, FUSE_WEIGHT_BUTTERFLY, OLD_FENCE

  #177·MarkRose opened Oct 26, 2026·

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• -tune: decide FP64 vs NTT inside the exponent range when it leaves out 141M

  #176·MarkRose opened Oct 26, 2026·

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• Odd middles 33 and 25 (opt-in): FP64 wins at 156M and 232M

  #174·MarkRose opened Oct 26, 2026·

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• FP64 tabMul: -use DD_TRIG=1 multiplies by hi + lo twiddles

  #173·MarkRose opened Oct 26, 2026·

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• Single-wide tailSquare: -use TAIL_RELABEL=1 relabels the partner line's lanes instead of reversing it in LDS

  #172·MarkRose opened Oct 26, 2026·

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• carryFused: -use CS_RING=R keeps the carry shuttle in a ring of R groups' slots

  #170·MarkRose opened Oct 26, 2026·

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• FP64/FP32 middles of radix 17 and 19 (opt-in)

  #169·MarkRose opened Oct 26, 2026·

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• FFT64 PFA middles as middle variant 3 (opt-in)

  #168·MarkRose opened Oct 26, 2026·

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• FP64 middle variant 2: middle twiddles from exact tables

  #167·MarkRose opened Oct 26, 2026·

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• Default to INPLACE=2 on wave32 AMD (RDNA)

  #166·MarkRose opened Oct 26, 2026·

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• Variant 2: -use BCAST_SLOT_W/H=1 broadcasts the f > 1 twiddles through a private LDS slot

  #165·MarkRose opened Oct 26, 2026·

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