いくつかの機能追加

ISA.h

@@ -39,7 +39,8 @@ typedef void (CPU::*alu_funcpr)(void);
 #define OP_SWL		42
 #define OP_SW		43
 #define OP_SWR		46
-/* OPCODE 44,45,47 are reserved */
+#define OP_CACHE	47
+/* OPCODE 44,45 are reserved */
 #define OP_LWC0		48
 #define OP_LWC1		49
 #define OP_LWC2		50
@@ -131,7 +132,7 @@ static operand_decodepr firstSrcDecTable[64] = {
 	NULL, NULL, NULL, NULL, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg,
 	CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg,
 	CPU::rs, CPU::rs, CPU::rs, CPU::rs, CPU::rs, CPU::rs, CPU::rs,CPU::no_reg,
-	CPU::rs, CPU::rs, CPU::rs, CPU::rs,CPU::no_reg,CPU::no_reg, CPU::rs, CPU::no_reg,
+	CPU::rs, CPU::rs, CPU::rs, CPU::rs,CPU::no_reg,CPU::no_reg, CPU::rs, CPU::rs,
 	CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg,
 	CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg, CPU::no_reg
 };
@@ -234,7 +235,7 @@ static bool mem_write_flag[64] = {
 };
 
 //indexed by opcode
-//flag of mem write
+//flag of mem read
 static bool mem_read_flag[64] = {
 	false, false, false, false, false, false, false, false,
 	false, false, false, false, false, false, false, false,
@@ -254,7 +255,7 @@ static bool RI_flag[64] = {
 	false, false, false, false, true , true , true , true ,
 	true , true , true , true , true , true , true , true ,
 	false, false, false, false, false, false, false, true ,
-	false, false, false, false, true , true , false, true ,
+	false, false, false, false, true , true , false, false ,
 	false, false, false, false, true , true , true , true ,
 	false, false, false, false, true , true , true , true
 };
@@ -271,6 +272,14 @@ static bool RI_special_flag[64] = {
 	true , true , true , true , true , true , true , true
 };
 
+//indexed by cache op operand (rt)
+static bool RI_cache_op_flag[32] = {
+	true, false, true, true, false, false, true, true,
+	true, false, true, true, true, true, true, true,
+	true, false, false, false, false, false, false, false,
+	false, false, false, false, false, false, false, false
+};
+
 //indexed by funct
 static bool mul_div_flag[64] = {
 	false, false, false, false, false, false, false, false,

Makefile

@@ -1,10 +1,10 @@
 # Config
 SYSCONFDIR = "."
-DEFS = -DHAVE_CONFIG_H
 DEFAULT_INCLUDES = -I.
 INCLUDES =
 EXEEXT =
 PACKAGE = cube_sim
+DEFS = -DHAVE_CONFIG_H
 MAKE = make
 
 # commands & flags
@@ -39,7 +39,7 @@ SOURCES = cpu.cc cpzero.cc devicemap.cc \
   types.h endiantest.h fileutils.h fpu.h interactor.h testdev.h \
   rs232c.h cache.h busarbiter.h routerinterface.cc routerinterface.h router.cc router.h \
   accelerator.h accelerator.cc acceleratorcore.h acceleratorcore.cc \
-  remoteram.h remoteram.cc
+  remoteram.h remoteram.cc cma.h cma.cc cmacore.cc cmacore.h cmaAddressMap.h
 
 OBJECTS = cpu.$(OBJEXT) cpzero.$(OBJEXT) devicemap.$(OBJEXT) \
 	mapper.$(OBJEXT) options.$(OBJEXT) range.$(OBJEXT) \
@@ -53,6 +53,7 @@ OBJECTS = cpu.$(OBJEXT) cpzero.$(OBJEXT) devicemap.$(OBJEXT) \
 	testdev.$(OBJEXT) rs232c.$(OBJEXT) cache.$(OBJEXT) busarbiter.$(OBJEXT) \
   routerinterface.${OBJEXT} router.${OBJEXT} \
   remoteram.${OBJEXT} accelerator.${OBJEXT} \
+  cma.${OBJEXT} cmacore.${OBJEXT}
 
 LDADD = libopcodes_mips/libopcodes_mips.a
 
@@ -91,7 +92,7 @@ cpu.o: cpu.cc cpu.h deviceexc.h accesstypes.h types.h config.h state.h \
   options.h \
   excnames.h error.h gccattr.h remotegdb.h fileutils.h stub-dis.h \
   libopcodes_mips/bfd.h libopcodes_mips/ansidecl.h \
-  libopcodes_mips/symcat.h libopcodes_mips/dis-asm.h ISA.h
+  libopcodes_mips/symcat.h libopcodes_mips/dis-asm.h ISA.h cacheinstr.h
 
 cpzero.o: cpzero.cc cpzero.h tlbentry.h config.h cpzeroreg.h types.h \
   mapper.h range.h accesstypes.h \
@@ -217,7 +218,7 @@ rs232c.o: rs232c.cc rs232c.h deviceint.h intctrl.h types.h config.h \
 cache.o: cache.cc cache.h \
   types.h config.h deviceexc.h accesstypes.h state.h vmips.h \
   mapper.h range.h \
-  excnames.h
+  excnames.h cacheinstr.h
 
 busarbiter.o: busarbiter.cc busarbiter.h
 
@@ -231,3 +232,9 @@ accelerator.o: accelerator.h accelerator.cc acceleratorcore.h range.h\
                router.h error.h options.h vmips.h
 
 remoteram.o: remoteram.cc remoteram.h accelerator.h memorymodule.h
+
+cma.o: cma.cc cma.h accelerator.h memorymodule.h accesstypes.h\
+         types.h cmacore.h cmaAddressMap.h
+
+cmacore.o: cmacore.h cmacore.cc cmaAddressMap.h memorymodule.h \
+            accelerator.h acceleratorcore.h

accelerator.cc

@@ -50,9 +50,9 @@ Range * LocalMapper::find_mapping_range(uint32 laddr)
 uint32 LocalMapper::fetch_word(uint32 laddr)
 {
 	Range *l = find_mapping_range(laddr);
-	uint32 offset = laddr - l->getBase();
 
 	if (l != NULL) {
+		uint32 offset = laddr - l->getBase();
 		return l->fetch_word(offset, DATALOAD, NULL);
 	} else {
 		if (machine->opt->option("dbemsg")->flag) {
@@ -65,9 +65,9 @@ uint32 LocalMapper::fetch_word(uint32 laddr)
 void LocalMapper::store_word(uint32 laddr, uint32 data)
 {
 	Range *l = find_mapping_range(laddr);
-	uint32 offset = laddr - l->getBase();
 
 	if (l != NULL) {
+		uint32 offset = laddr - l->getBase();
 		l->store_word(offset, data, NULL);
 	} else {
 		if (machine->opt->option("dbemsg")->flag) {
@@ -147,8 +147,8 @@ void NetworkInterfaceConfig::store_word(uint32 offset, uint32 data, DeviceExc *c
 }
 
 /*******************************  CubeAccelerator  *******************************/
-CubeAccelerator::CubeAccelerator(uint32 node_ID, Router* upperRouter, uint32 config_addr_base, bool dmac_en_)
-	: dmac_en(dmac_en_)
+CubeAccelerator::CubeAccelerator(uint32 node_ID_, Router* upperRouter, uint32 config_addr_base, bool dmac_en_)
+	: node_ID(node_ID_), dmac_en(dmac_en_)
 {
 	//make router ports
 	rtRx = new RouterPortSlave(iready); //receiver
@@ -166,6 +166,8 @@ CubeAccelerator::CubeAccelerator(uint32 node_ID, Router* upperRouter, uint32 con
 	nif_config = new NetworkInterfaceConfig(config_addr_base);
 	localBus->map_at_local_address(nif_config, config_addr_base);
 
+	done_signal_ptr = std::bind(&CubeAccelerator::done_signal, this, std::placeholders::_1);
+
 }
 
 void CubeAccelerator::nif_step()
@@ -301,7 +303,7 @@ void CubeAccelerator::nif_step()
 		case CNIF_DONE:
 			if(rtTx->slaveReady(nif_config->getVCdone())) {
 				RouterUtils::make_head_flit(&sflit, DONE_NOTIF_ADDR, MTYPE_DONE,
-											nif_config->getVCdone(), reg_dst, 0, true);
+											nif_config->getVCdone(), node_ID, 0, true);
 				rtTx->send(&sflit, nif_config->getVCdone());
 				if (dma_after_done_en & (nif_config->getDMAlen() > 0)) {
 					nif_next_state = CNIF_DMA_HEAD;
@@ -364,4 +366,4 @@ void CubeAccelerator::done_signal(bool dma_enable)
 {
 	done_pending = true;
 	dma_after_done_en = dma_enable;
-}
+}

accelerator.h

@@ -117,10 +117,8 @@ class CubeAccelerator {
 	RouterPortMaster *rtTx;
 	Router *localRouter;
 
-	//submodules
-	AcceleratorCore *core_module;
-
 	//Cube nif
+	int node_ID;
 	NetworkInterfaceConfig* nif_config;
 	uint32 reg_mema, reg_mtype, reg_vch, reg_src, reg_dst;
 	int dcount;
@@ -136,12 +134,17 @@ class CubeAccelerator {
 
 protected:
 	//constructor
-	CubeAccelerator(uint32 node_ID, Router* upperRouterm,
+	CubeAccelerator(uint32 node_ID_, Router* upperRouter,
 		uint32 config_addr_base = NIF_CONFIG_BASE, bool dmac_en_ = true);
 
 	//data/address bus
 	LocalMapper* localBus;
 
+	//submodules
+	AcceleratorCore *core_module;
+
+	SIGNAL_PTR done_signal_ptr;
+
 public:
 	//destructor
 	virtual ~CubeAccelerator() {};

acceleratorcore.h

@@ -1,10 +1,24 @@
 #ifndef _ACCELERATORCORE_H_
 #define _ACCELERATORCORE_H_
 
+#include <functional>
+#include "accelerator.h"
+
+typedef std::function<void(bool)> SIGNAL_PTR;
+
+class LocalMapper;
+class CubeAccelerator;
+
 class AcceleratorCore {
 private:
 
+protected:
+	LocalMapper *bus;
+	SIGNAL_PTR done_signal;
+
 public:
+	AcceleratorCore(LocalMapper *bus_, SIGNAL_PTR done_signal_)
+	: bus(bus_), done_signal(done_signal_) {};
 	virtual void step() = 0;
 	virtual void reset() = 0;
 };

cache.cc

@@ -50,7 +50,7 @@ void Cache::step()
 		last_state_update_time = machine->num_cycles;
 	}
 
-	if (status == CACHE_WB) {
+	if (status == CACHE_WB || status == CACHE_OP_WB) {
 		cache_wb();
 	} else if (status == CACHE_FETCH) {
 		cache_fetch();
@@ -115,7 +115,7 @@ void Cache::request_block(uint32 addr, int mode, DeviceExc* client)
 
 	//if cache is working or bus is busy, request is ignored
 	if (status == CACHE_IDLE && physmem->acquire_bus(client)) {
-		//find free block and LRU block
+		//find free block or LRU block
 		for (way = 0; way < way_size; way++) {
 			if (blocks[least_recent_used_way][index].last_access >
 					blocks[way][index].last_access) {
@@ -148,7 +148,7 @@ void Cache::request_block(uint32 addr, int mode, DeviceExc* client)
 		}
 #endif
 		// regist replaced cache block & status
-		cache_op_state = new CacheOpState{word_size, addr, way, index, mode, client};
+		cache_op_state = new CacheOpState{word_size, addr, way, index, mode, false, client};
 		cache_miss_counts++;
 	}
 }
@@ -176,8 +176,19 @@ void Cache::cache_wb()
 
 		if (--cache_op_state->counter == 0) {
 			//finish write back
-			next_status = CACHE_FETCH;
-			cache_op_state->counter = word_size;
+			if (status == CACHE_OP_WB) {
+				//no need to fetch block
+				blocks[way][index].dirty = false;
+				if (cache_op_state->last_invalidate) {
+					blocks[way][index].valid = false;
+				}
+				next_status = CACHE_IDLE;
+				delete cache_op_state;
+				physmem->release_bus(cache_op_state->client);
+			} else {
+				next_status = CACHE_FETCH;
+				cache_op_state->counter = word_size;
+			}
 			cache_wb_counts++;
 		}
 	}
@@ -220,6 +231,123 @@ void Cache::cache_fetch()
 	}
 }
 
+bool Cache::exec_cache_op(uint16 opcode, uint32 addr, DeviceExc* client)
+{
+	uint32 tag, index, way, offset;
+	uint32 least_recent_used_way = 0;
+	int mode = DATALOAD;
+	bool last_invalidate = false;
+	bool stall = false;
+	bool find;
+
+	//if it causes cpu stall, return false
+	if (status == CACHE_IDLE && physmem->acquire_bus(client)) {
+		switch (opcode) {
+			//invalidate by index
+			case ICACHE_OP_IDX_INV:
+				mode = INSTFETCH;
+			case DCACHE_OP_IDX_INV:
+				fprintf(stderr, "cache index invalidate not implemented\n");
+				break;
+			//write back & invalidate by index
+			case DCACHE_OP_IDX_WB:
+				fprintf(stderr, "cache index writeback not implemented\n");
+				break;
+			case DCACHE_OP_IDX_WBINV:
+				fprintf(stderr, "cache index writeback, invalidate not implemented\n");
+				break;
+			//load tag by index
+			case ICACHE_OP_IDX_LTAG:
+				mode = INSTFETCH;
+			case DCACHE_OP_IDX_LTAG:
+				fprintf(stderr, "cache tag load not implemented\n");
+				break;
+			//store tag by inedx
+			case ICACHE_OP_IDX_STAG:
+				mode = INSTFETCH;
+			case DCACHE_OP_IDX_STAG:
+				fprintf(stderr, "cache tag store not implemented\n");
+				break;
+			//force write back by index
+			case DCACHE_OP_IDX_FWB:
+				fprintf(stderr, "cache index force writeback not implemented\n");
+				break;
+			//force write back & invalidate by index
+			case DCACHE_OP_IDX_FWBINV:
+				fprintf(stderr, "cache index force writeback, invalidate not implemented\n");
+				break;
+			//setline
+			case DCACHE_OP_SETLINE:
+				if (!cache_hit(addr, index, way, offset)) {
+					addr_separete(addr, tag, index, offset);
+					//find free block or oldest block
+					for (way = 0, find = false; way < way_size; way++) {
+						if (!blocks[way][index].valid) {
+							find = true;
+							break;
+						}
+						if (blocks[least_recent_used_way][index].last_access >
+								blocks[way][index].last_access) {
+							//update
+							least_recent_used_way = way;
+						}
+					}
+					if (!find) {
+						way = least_recent_used_way;
+						if (blocks[way][index].dirty) {
+							next_status = CACHE_OP_WB;
+						}
+					} else {
+						blocks[way][index].valid = true;
+						//overwrite tag
+						blocks[way][index].tag = tag;
+						blocks[way][index].dirty = false;
+					}
+				}
+				break;
+			//invalidate by cache hit
+			case ICACHE_OP_HIT_INV:
+				mode = INSTFETCH;
+			case DCACHE_OP_HIT_INV:
+				if (cache_hit(addr, index, way, offset)) {
+					blocks[way][index].valid = false;
+				}
+				break;
+			//(force) write back (&invalidate) by cache hit
+			case DCACHE_OP_HIT_WBINV:
+			case DCACHE_OP_HIT_FWBINV:
+				last_invalidate = true;
+			case DCACHE_OP_HIT_WB:
+			case DCACHE_OP_HIT_FWB:
+				if (cache_hit(addr, index, way, offset)) {
+					if (blocks[way][index].dirty) {
+						next_status = CACHE_OP_WB;
+					} else if (opcode == DCACHE_OP_HIT_FWB || opcode == DCACHE_OP_HIT_INV) {
+						next_status = CACHE_OP_WB;
+					}
+				}
+				break;
+			//change
+			case DCACHE_OP_CHANGE:
+				fprintf(stderr, "cache change not implemented\n");
+				break;
+			//reverse change
+			case DCACHE_OP_RCHANGE:
+				fprintf(stderr, "cache reverse change not implemented\n");
+				break;
+		}
+		if (next_status == CACHE_OP_WB) {
+			cache_op_state = new CacheOpState{word_size, addr, way, index, mode, last_invalidate, client};
+			stall = true;
+		}
+	} else {
+		//cache is working
+		stall = true;
+	}
+
+	return !stall;
+}
+
 uint32 Cache::fetch_word(uint32 addr, int32 mode, DeviceExc *client)
 {
 	uint32 offset;