Computer-Architecture-Processor

This Computer Architecture project is to design and implement a simple 5-stage pipelined processor, Harvard. The design should conform to the ISA specification described. The processor in this project has a RISC-like instruction set architecture. There are eight 4-byte general purpose registers; R0, till R7. Another two general purpose registers, One works as a program counter (PC). And the other, works as a stack pointer (SP); and hence; points to the top of the stack. The initial value of SP is (2^20-2). The memory address space is 1 MB of 16-bit width and is word addressable. ( N.B. word = 2 bytes). You are allowed to make the data bus 32 bits to access two consecutive words.