[LLVM Pulldown] Bump to rev 50351218b3a4687079fe79f932aac0e00d5d990f

build_tools/llvm_version.txt

@@ -1 +1 @@
-19b28074618c92fa4c4281eeee67c715abebbfd7
+50351218b3a4687079fe79f932aac0e00d5d990f

build_tools/patches/0001-Add-support-for-VectorAnyINTEL-capability.patch

@@ -1,7 +1,7 @@
-From 887ae8599b205921bc4fd34da3c1de767f5568ae Mon Sep 17 00:00:00 2001
+From 1dd1130e8647473448ca9ce808e7bc6efa424675 Mon Sep 17 00:00:00 2001
 From: Garra1980 <igor.zamyatin@intel.com>
-Date: Tue, 23 Sep 2025 21:22:18 +0200
-Subject: [PATCH] Add support for VectorAnyINTEL capability
+Date: Mon, 5 Jan 2026 17:46:15 +0100
+Subject: [PATCH] Add-support-for-VectorAnyINTEL-capability
 
 ---
  .../mlir/Dialect/SPIRV/IR/SPIRVBase.td        |  11 +-
@@ -24,7 +24,7 @@ Subject: [PATCH] Add support for VectorAnyINTEL capability
  17 files changed, 324 insertions(+), 68 deletions(-)
 
 diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
-index 0e42d08cdb1f..f821b0d2e59b 100644
+index ecbbf39a534e..d6a72472bd1b 100644
 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
 +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
 @@ -4240,7 +4240,14 @@ def SPIRV_BFloat16KHR : TypeAlias<BF16, "BFloat16">;
@@ -53,10 +53,10 @@ index 0e42d08cdb1f..f821b0d2e59b 100644
  class SPIRV_ScalarOrVectorOf<Type type> :
      AnyTypeOf<[type, SPIRV_VectorOf<type>]>;
 diff --git a/mlir/include/mlir/IR/CommonTypeConstraints.td b/mlir/include/mlir/IR/CommonTypeConstraints.td
-index 6b4e3dd60319..987b33c055e9 100644
+index 0fb4837e528b..a33b18e8c868 100644
 --- a/mlir/include/mlir/IR/CommonTypeConstraints.td
 +++ b/mlir/include/mlir/IR/CommonTypeConstraints.td
-@@ -654,6 +654,92 @@ class ScalableVectorOfRankAndLengthAndType<list<int> allowedRanks,
+@@ -696,6 +696,92 @@ class ScalableVectorOfRankAndLengthAndType<list<int> allowedRanks,
    ScalableVectorOfLength<allowedLengths>.summary,
    "::mlir::VectorType">;
 
@@ -150,7 +150,7 @@ index 6b4e3dd60319..987b33c055e9 100644
  // Negative values for `n` index in reverse.
  class ShapedTypeWithNthDimOfSize<int n, list<int> allowedSizes> : Type<
 diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
-index c8efdf009422..5236dc299f81 100644
+index 22b57d6c0821..8f02dd856d4e 100644
 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
 +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
 @@ -186,9 +186,12 @@ static Type parseAndVerifyType(SPIRVDialect const &dialect,
@@ -169,7 +169,7 @@ index c8efdf009422..5236dc299f81 100644
        return Type();
      }
 diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
-index 7e9a80e7d73a..1db6233cf73f 100644
+index 53a48abe5ad0..4c39a7c83281 100644
 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
 +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
 @@ -186,9 +186,10 @@ bool CompositeType::classof(Type type) {
@@ -178,15 +178,15 @@ index 7e9a80e7d73a..1db6233cf73f 100644
  bool CompositeType::isValid(VectorType type) {
 -  return type.getRank() == 1 &&
 -         llvm::is_contained({2, 3, 4, 8, 16}, type.getNumElements()) &&
--         llvm::isa<ScalarType>(type.getElementType());
+-         isa<ScalarType>(type.getElementType());
 +  // Number of elements should be between [2 to 2^32 - 1].
-+  return type.getRank() == 1 && mlir::isa<ScalarType>(type.getElementType()) &&
++  return type.getRank() == 1 && isa<ScalarType>(type.getElementType()) &&
 +         type.getNumElements() >= 2 &&
 +         type.getNumElements() <= std::numeric_limits<uint32_t>::max();
  }
 
  Type CompositeType::getElementType(unsigned index) const {
-@@ -221,8 +222,23 @@ void TypeCapabilityVisitor::addConcrete(VectorType type) {
+@@ -218,8 +219,23 @@ void TypeCapabilityVisitor::addConcrete(VectorType type) {
 
    int64_t vecSize = type.getNumElements();
    if (vecSize == 8 || vecSize == 16) {
@@ -213,7 +213,7 @@ index 7e9a80e7d73a..1db6233cf73f 100644
  }
 
 diff --git a/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp b/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
-index 122f61e0a66a..c6f37e9345ed 100644
+index 816226749463..31c590efcda3 100644
 --- a/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
 +++ b/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
 @@ -84,9 +84,13 @@ static std::optional<SmallVector<int64_t>> getTargetShape(VectorType vecType) {
@@ -385,7 +385,7 @@ index 122f61e0a66a..c6f37e9345ed 100644
  }
 
  static Type
-@@ -1693,16 +1780,18 @@ bool SPIRVConversionTarget::isLegalOp(Operation *op) {
+@@ -1694,16 +1781,18 @@ bool SPIRVConversionTarget::isLegalOp(Operation *op) {
    SmallVector<ArrayRef<spirv::Extension>, 4> typeExtensions;
    SmallVector<ArrayRef<spirv::Capability>, 8> typeCapabilities;
    for (Type valueType : valueTypes) {

build_tools/patches/0006-Add-SPIRV_ExecutionModeAttributesAttr.patch

@@ -1,9 +1,8 @@
-From a18280b49a33d421477db322d642aff187b029f8 Mon Sep 17 00:00:00 2001
-From: Dimple Prajapati <dimpalben.r.prajapati@intel.com>
-Date: Tue, 7 May 2024 23:26:34 +0000
-Subject: [PATCH] Add SPIRV_ExecutionModeAttributesAttr
+From ab51a97f5358afe72bfce6483a3416a50dc40018 Mon Sep 17 00:00:00 2001
+From: Garra1980 <igor.zamyatin@intel.com>
+Date: Mon, 5 Jan 2026 17:51:39 +0100
+Subject: [PATCH] Add-SPIRV_ExecutionModeAttributesAttr
 
-add spirv.ExecutionMode Op during GPUToSPIRV Pass lowering
 ---
  .../mlir/Dialect/SPIRV/IR/SPIRVAttributes.td   | 11 +++++++++++
  .../mlir/Dialect/SPIRV/IR/TargetAndABI.h       |  8 ++++++++
@@ -13,7 +12,7 @@ add spirv.ExecutionMode Op during GPUToSPIRV Pass lowering
  5 files changed, 55 insertions(+)
 
 diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.td
-index 3a11284da051..1267ecd251ae 100644
+index 1bc3c63646fd..cf5b5ffa451d 100644
 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.td
 +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.td
 @@ -56,6 +56,17 @@ def SPIRV_LinkageAttributesAttr : SPIRV_Attr<"LinkageAttributes", "linkage_attri
@@ -54,10 +53,10 @@ index 24574bfaf619..f64f99294038 100644
  } // namespace mlir
 
 diff --git a/mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp b/mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
-index d7885e035959..5195035f088f 100644
+index c33a903d0339..a6578465abac 100644
 --- a/mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
 +++ b/mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
-@@ -343,6 +343,20 @@ LogicalResult GPUFuncOpConversion::matchAndRewrite(
+@@ -346,6 +346,20 @@ LogicalResult GPUFuncOpConversion::matchAndRewrite(
      return failure();
    newFuncOp->removeAttr(
        rewriter.getStringAttr(gpu::GPUDialect::getKernelFuncAttrName()));
@@ -79,25 +78,25 @@ index d7885e035959..5195035f088f 100644
  }
 
 diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
-index 65aaafa55386..b9f906ada3ee 100644
+index 8f02dd856d4e..dfb13c173596 100644
 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
 +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
-@@ -948,6 +948,10 @@ LogicalResult SPIRVDialect::verifyOperationAttribute(Operation *op,
+@@ -1026,6 +1026,10 @@ LogicalResult SPIRVDialect::verifyOperationAttribute(Operation *op,
    } else if (symbol == spirv::getTargetEnvAttrName()) {
-     if (!llvm::isa<spirv::TargetEnvAttr>(attr))
+     if (!isa<spirv::TargetEnvAttr>(attr))
        return op->emitError("'") << symbol << "' must be a spirv::TargetEnvAttr";
 +  } else if (symbol == spirv::getExecutionModeFuncAttrName()) {
-+    if (!llvm::isa<spirv::ExecutionModeFuncAttributeAttr>(attr))
++    if (!isa<spirv::ExecutionModeFuncAttributeAttr>(attr))
 +      return op->emitError("'")
 +             << symbol << "' must be a spirv::ExecutionModeFuncAttributeAttr";
    } else {
      return op->emitError("found unsupported '")
             << symbol << "' attribute on operation";
 diff --git a/mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp b/mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
-index bbc318e17300..56251a8f3990 100644
+index 8c52ba8b8583..864fc75c53b1 100644
 --- a/mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
 +++ b/mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
-@@ -242,3 +242,21 @@ spirv::getMemoryModel(spirv::TargetEnvAttr targetAttr) {
+@@ -238,3 +238,21 @@ spirv::getMemoryModel(spirv::TargetEnvAttr targetAttr) {
    }
    return failure();
  }

build_tools/patches/0014-Add-32-64-and-128-length-vector-as-supported-vectors.patch

@@ -1,18 +1,14 @@
-From 27bd5d19a0f122d9acded716fe936d07416e1308 Mon Sep 17 00:00:00 2001
-From: "Shahneous Bari, Md Abdullah" <md.abdullah.shahneous.bari@intel.com>
-Date: Wed, 17 Dec 2025 14:21:48 +0000
-Subject: [PATCH] Add 32, 64 and 128 length vector as supported vectors.
+From 0f49dfa51b379d1197b290e810ce2d3d178b5dde Mon Sep 17 00:00:00 2001
+From: Garra1980 <igor.zamyatin@intel.com>
+Date: Mon, 5 Jan 2026 15:48:16 +0100
+Subject: [PATCH] Add-32-64-and-128-length-vector-as-supported-vectors
 
-This is needed to support large loads/stores using OpenCL intrinsics in
-MLIR workflow.
-THIS IS A HACK and temporary solution,
-need to re-visit this with better solution later.
 ---
- llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp | 81 ++++++++++++++------
- 1 file changed, 59 insertions(+), 22 deletions(-)
+ llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp | 82 +++++++++++++++-----
+ 1 file changed, 61 insertions(+), 21 deletions(-)
 
 diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
-index 30703ee40be0..2f3baa1b6c7e 100644
+index 590182731b00..0d9f4df374f9 100644
 --- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
 +++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
 @@ -50,6 +50,28 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
@@ -44,20 +40,15 @@ index 30703ee40be0..2f3baa1b6c7e 100644
    const LLT v16s64 = LLT::fixed_vector(16, 64);
    const LLT v16s32 = LLT::fixed_vector(16, 32);
    const LLT v16s16 = LLT::fixed_vector(16, 16);
-@@ -99,41 +121,53 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
+@@ -100,16 +122,22 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
 
    // TODO: remove copy-pasting here by using concatenation in some way.
    auto allPtrsScalarsAndVectors = {
--      p0,    p1,    p2,    p3,    p4,     p5,     p6,    p7,    p8,
--      p9,    p10,   p11,   p12,   s1,     s8,     s16,   s32,   s64,
--      v2s1,  v2s8,  v2s16, v2s32, v2s64,  v3s1,   v3s8,  v3s16, v3s32,
--      v3s64, v4s1,  v4s8,  v4s16, v4s32,  v4s64,  v8s1,  v8s8,  v8s16,
--      v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
--
--  auto allVectors = {v2s1,  v2s8,   v2s16,  v2s32, v2s64, v3s1,  v3s8,
--                     v3s16, v3s32,  v3s64,  v4s1,  v4s8,  v4s16, v4s32,
--                     v4s64, v8s1,   v8s8,   v8s16, v8s32, v8s64, v16s1,
--                     v16s8, v16s16, v16s32, v16s64};
+-      p0,    p1,    p2,    p3,    p4,    p5,     p6,     p7,    p8,
+-      p9,    p10,   p11,   p12,   p13,   s1,     s8,     s16,   s32,
+-      s64,   v2s1,  v2s8,  v2s16, v2s32, v2s64,  v3s1,   v3s8,  v3s16,
+-      v3s32, v3s64, v4s1,  v4s8,  v4s16, v4s32,  v4s64,  v8s1,  v8s8,
+-      v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
 +      p0,     p1,     p2,      p3,      p4,     p5,     p6,     p7,     p8,
 +      p9,     p10,    p11,     p12,     s1,     s8,     s16,    s32,    s64,
 +      s128,   v2s1,   v2s8,    v2s16,   v2s32,  v2s64,  v3s1,   v3s8,   v3s16,
@@ -74,9 +65,15 @@ index 30703ee40be0..2f3baa1b6c7e 100644
 +                     v32s32, v32s64, v64s1,   v64s8,   v64s16, v64s32, v64s64,
 +                     v128s1, v128s8, v128s16, v128s32, v128s64};
 
+-  auto allVectors = {v2s1,  v2s8,   v2s16,  v2s32, v2s64, v3s1,  v3s8,
+-                     v3s16, v3s32,  v3s64,  v4s1,  v4s8,  v4s16, v4s32,
+-                     v4s64, v8s1,   v8s8,   v8s16, v8s32, v8s64, v16s1,
+-                     v16s8, v16s16, v16s32, v16s64};
+
    auto allShaderVectors = {v2s1, v2s8, v2s16, v2s32, v2s64,
                             v3s1, v3s8, v3s16, v3s32, v3s64,
-                            v4s1, v4s8, v4s16, v4s32, v4s64};
+@@ -118,25 +146,32 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
+   auto allScalars = {s1, s8, s16, s32, s64};
 
    auto allScalarsAndVectors = {
 -      s1,    s8,    s16,   s32,   s64,    s128,   v2s1,  v2s8,
@@ -116,28 +113,30 @@ index 30703ee40be0..2f3baa1b6c7e 100644
 +      v32s1,  v32s8,  v32s16, v32s32,  v32s64,  v64s1,  v64s8,  v64s16, v64s32,
 +      v64s64, v128s1, v128s8, v128s16, v128s32, v128s64};
 
-   auto allFloatAndIntScalarsAndPtrs = {s8, s16, s32, s64, p0, p1,  p2,  p3, p4,
-                                        p5, p6,  p7,  p8,  p9, p10, p11, p12};
-@@ -170,7 +204,9 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
+   auto allFloatAndIntScalarsAndPtrs = {s8, s16, s32, s64, p0,  p1,
+                                        p2, p3,  p4,  p5,  p6,  p7,
+@@ -174,7 +209,9 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
    // shader execution models, vector sizes are strictly limited to 4. In
    // non-shader contexts, vector sizes of 8 and 16 are also permitted, but
    // arbitrary sizes (e.g., 6 or 11) are not.
 -  uint32_t MaxVectorSize = ST.isShader() ? 4 : 16;
 +
 +  // @IMEX, make the max vector size to be 128 for now.
 +  uint32_t MaxVectorSize = ST.isShader() ? 4 : 128;
+   LLVM_DEBUG(dbgs() << "MaxVectorSize: " << MaxVectorSize << "\n");
 
    for (auto Opc : getTypeFoldingSupportedOpcodes()) {
-     if (Opc != G_EXTRACT_VECTOR_ELT)
-@@ -531,7 +567,8 @@ bool SPIRVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
-     LLT DstTy = MRI.getType(DstReg);
-     LLT SrcTy = MRI.getType(SrcReg);
-
--    int32_t MaxVectorSize = ST.isShader() ? 4 : 16;
-+    // @IMEX make the max vector size to be 128
-+    int32_t MaxVectorSize = ST.isShader() ? 4 : 128;
-
-     bool DstNeedsLegalization = false;
-     bool SrcNeedsLegalization = false;
+@@ -579,7 +616,10 @@ static bool needsVectorLegalization(const LLT &Ty, const SPIRVSubtarget &ST) {
+   if (!Ty.isVector())
+     return false;
+   unsigned NumElements = Ty.getNumElements();
+-  unsigned MaxVectorSize = ST.isShader() ? 4 : 16;
++
++  // @IMEX make the max vector size to be 128
++  int32_t MaxVectorSize = ST.isShader() ? 4 : 128;
++
+   return (NumElements > 4 && !isPowerOf2_32(NumElements)) ||
+          NumElements > MaxVectorSize;
+ }
 --
-2.43.0
+2.34.1