De10 implementation

.gitignore

@@ -1,8 +1,10 @@
 work/
 *.txt
 dumpfile
-risc_test_program/merge_sort
-risc_test_program/risc_test
+sram_dumpfile
+merge_sort
+risc_test
+blinky
 
 # ignore ModelSim generated files and directories (temp files and so on)
 [_@]*
@@ -26,4 +28,53 @@ wlf*
 cov*/
 transcript*
 sc_dpiheader.h
-vsim.dbg
+vsim.
+
+# ignore Quartus II generated files
+*_generation_script*
+*_inst.vhd
+*.bak
+*.cmp
+*.cdf
+*.done
+*.eqn
+*.hex
+*.html
+*.jdi
+*.jpg
+*.mif
+*.pin
+*.pof
+*.ptf.*
+*.qar
+*.qarlog
+*.qws
+*.rpt
+*.smsg
+*.sof
+*.sopc_builder
+*.summary
+*.tcl
+*.txt # Explicitly add any text files used
+*~
+*example*
+*sopc_*
+# *.sdc # I want those timing files
+
+# ignore Quartus II generated folders
+*/db/
+*/incremental_db/
+*/simulation/
+*/timing/
+*/testbench/
+*/*_sim/
+incremental_db/
+db/
+_output_files/
+PLLJ_PLLSPE_INFO.txt
+
+/xpacks
+/.vscode
+/build
+*.o
+/.pytest_cache

Makefile

@@ -0,0 +1,35 @@
+DIR := ./xpacks/.bin
+SRC_DIR := ./tests/src
+HEX_DIR := ./tests/hex
+OBJ_DIR := ./tests/obj
+
+CC := $(DIR)/riscv-none-elf-gcc
+PYTHON := python3
+OBJDUMP := $(DIR)/riscv-none-elf-objdump
+OBJCOPY := $(DIR)/riscv-none-elf-objcopy
+MEM_WORD_LENGTH := 4
+
+CFLAGS := -O0 -ffunction-sections -Xlinker -g -T./tests/risc.ld -mbig-endian -nostdlib -ffreestanding -fno-pie -fno-stack-protector -Wall -mno-fdiv -march=rv32i -mabi=ilp32
+
+SRCS = $(wildcard $(SRC_DIR)/*.c)
+
+PROGS = $(patsubst ${SRC_DIR}/%.c,%,$(SRCS))
+.PHONY: $(PROGS)
+
+all: $(PROGS)
+
+$(PROGS):
+	$(CC) $(CFLAGS) -o $(OBJ_DIR)/[email protected] $(SRC_DIR)/[email protected]
+	$(OBJCOPY) --remove-section=.comment --reverse-bytes=$(MEM_WORD_LENGTH) \
+		--verilog-data-width $(MEM_WORD_LENGTH) \
+		$(OBJ_DIR)/[email protected] -O verilog $(HEX_DIR)/[email protected]
+
+test:
+	python3 -m pytest ./tests
+
+dump:
+	$(OBJDUMP) -D --disassembler-options=no-aliases $(OBJ_DIR)/$(FILE)
+
+clean:
+	rm -r tests/obj/* tests/hex/* build
+

README.md

@@ -1,6 +1,9 @@
 # riscv-processor
-RISCV processor in verilog.
 
-Made for educational purposes.
-
-Test programs are in risc\_test\_program.
+## TODO:
+1. Fix sram in simulation to make sure it works properly.
+2. Make sure logic works on MAX10
+3. Implement Linter and automatic formatter for Verilog
+4. Design Cache
+5. Refactor Verilog code to look neater.
+6. Get SDRAM controller working