Cyclone V Nios II

Nios II RISC embedded processor implementation for DE0-CV (Cyclone V)

Used IPs

• Nios II Processor
• Clock Bridge
• Reset Bridge
• On Chip Memory Intel FPGA IP
• JTAG UART Intel FPGA IP
• PIO (Parallel I/O) Intel FPGA IP

Requirements

• nios2eds
  https://www.terasic.com.tw/wiki/Getting_Start_Install_Eclipse_IDE_into_Nios_EDS
• WSL (Ubuntu 20.04 LTS) with dos2unix installed
  https://www.terasic.com.tw/wiki/Getting_Start_Install_WSL

Reference

• Nios II Hello World tutorial
  https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset02/nios-ii-hello-world-a10.pdf