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[FIRRTL][InferWidths] infer through send/resolve, test. (#3712)
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dtzSiFive authored Aug 15, 2022
1 parent 1315acf commit 570ad7c
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9 changes: 9 additions & 0 deletions lib/Dialect/FIRRTL/Transforms/InferWidths.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1518,6 +1518,15 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
}
})

.Case<RefSendOp>([&](auto op) {
declareVars(op.getResult(), op.getLoc());
constrainTypes(op.getResult(), op.getBase());
})
.Case<RefResolveOp>([&](auto op) {
declareVars(op.getResult(), op.getLoc());
constrainTypes(op.getResult(), op.getRef());
})

.Default([&](auto op) {
op->emitOpError("not supported in width inference");
mappingFailed = true;
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19 changes: 19 additions & 0 deletions test/Dialect/FIRRTL/infer-widths.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -801,4 +801,23 @@ firrtl.circuit "Foo" {
}

firrtl.module @Foo() {}

// CHECK-LABEL: @SubRef
// CHECK: out %x: !firrtl.ref<uint<2>>
firrtl.module private @SubRef(out %x: !firrtl.ref<uint>) {
%w = firrtl.wire : !firrtl.uint
%ref_w = firrtl.ref.send %w : !firrtl.uint
firrtl.connect %x, %ref_w : !firrtl.ref<uint>, !firrtl.ref<uint>

%c0_ui2 = firrtl.constant 0 : !firrtl.uint<2>
firrtl.connect %w, %c0_ui2 : !firrtl.uint, !firrtl.uint<2>
}
// CHECK-LABEL: @Ref
// CHECK: out x: !firrtl.ref<uint<2>>
// CHECK: %sub_x : !firrtl.ref<uint<2>>
firrtl.module @Ref(out %r : !firrtl.uint) {
%sub_x = firrtl.instance sub @SubRef(out x: !firrtl.ref<uint>)
%res = firrtl.ref.resolve %sub_x : !firrtl.ref<uint>
firrtl.connect %r, %res : !firrtl.uint, !firrtl.uint
}
}

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