[Arc] Fix arc.output verifier

llvm · May 14, 2023 · 76e7f63 · 76e7f63
1 parent 43e69a8
commit 76e7f63
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Showing 2 changed files with 52 additions and 32 deletions.
diff --git a/lib/Dialect/Arc/ArcOps.cpp b/lib/Dialect/Arc/ArcOps.cpp
@@ -131,26 +131,13 @@ bool DefineOp::isPassthrough() {
 //===----------------------------------------------------------------------===//
 
 LogicalResult OutputOp::verify() {
-  return success();
-
-  auto parent = cast<DefineOp>((*this)->getParentOp());
-  ArrayRef<Type> types = parent.getResultTypes();
-  OperandRange values = getOperands();
-  if (types.size() != values.size()) {
-    emitOpError("must have same number of operands as parent arc has results");
-    return failure();
-  }
-
-  for (size_t i = 0, e = types.size(); i < e; ++i) {
-    if (types[i] != values[i].getType()) {
-      emitOpError("output operand ")
-          << i << " type mismatch: arc requires " << types[i] << ", operand is "
-          << values[i].getType();
-      return failure();
-    }
-  }
+  auto *parent = (*this)->getParentOp();
+  TypeRange expectedTypes = parent->getResultTypes();
+  if (auto defOp = dyn_cast<DefineOp>(parent))
+    expectedTypes = defOp.getResultTypes();
 
-  return success();
+  TypeRange actualTypes = getOperands().getTypes();
+  return verifyTypeListEquivalence(*this, expectedTypes, actualTypes, "output");
 }
 
 //===----------------------------------------------------------------------===//
@@ -214,15 +201,8 @@ LogicalResult MemoryWritePortOp::verify() {
 //===----------------------------------------------------------------------===//
 
 LogicalResult ClockDomainOp::verifyRegions() {
-  if (failed(verifyTypeListEquivalence(*this, getBodyBlock().getArgumentTypes(),
-                                       getInputs().getTypes(), "input")))
-    return failure();
-  if (failed(verifyTypeListEquivalence(
-          *this, getOutputs().getTypes(),
-          getBodyBlock().getTerminator()->getOperandTypes(), "output")))
-    return failure();
-
-  return success();
+  return verifyTypeListEquivalence(*this, getBodyBlock().getArgumentTypes(),
+                                   getInputs().getTypes(), "input");
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/test/Dialect/Arc/basic-errors.mlir b/test/Dialect/Arc/basic-errors.mlir
@@ -159,6 +159,29 @@ arc.define @lut () -> () {
 
 // -----
 
+arc.define @lut () -> () {
+  %0 = arc.lut () : () -> i32 {
+    // expected-error @+1 {{incorrect number of outputs: expected 1, but got 0}}
+    arc.output
+  }
+  arc.output
+}
+
+// -----
+
+arc.define @lut () -> () {
+  %0 = arc.lut () : () -> i32 {
+    %1 = hw.constant 0 : i16
+    // expected-error @+3 {{output type mismatch: output #0}}
+    // expected-note @+2 {{expected type: 'i32'}}
+    // expected-note @+1 {{actual type: 'i16'}}
+    arc.output %1 : i16
+  }
+  arc.output
+}
+
+// -----
+
 arc.define @lut (%arg0: i32, %arg1: i8) -> () {
   // expected-note @+1 {{required by region isolation constraints}}
   %1 = arc.lut (%arg1, %arg0) : (i8, i32) -> i32 {
@@ -186,9 +209,9 @@ arc.define @lutSideEffects () -> i32 {
 // -----
 
 hw.module @clockDomainNumOutputs(%clk: i1) {
-  // expected-error @+1 {{incorrect number of outputs: expected 1, but got 0}}
   %0 = arc.clock_domain () clock %clk : () -> (i32) {
   ^bb0:
+    // expected-error @+1 {{incorrect number of outputs: expected 1, but got 0}}
     arc.output
   }
   hw.output
@@ -221,12 +244,12 @@ hw.module @clockDomainInputTypes(%clk: i1, %arg0: i16) {
 // -----
 
 hw.module @clockDomainOutputTypes(%clk: i1) {
-  // expected-error @+3 {{output type mismatch: output #0}}
-  // expected-note @+2 {{expected type: 'i32'}}
-  // expected-note @+1 {{actual type: 'i16'}}
   %0 = arc.clock_domain () clock %clk : () -> (i32) {
   ^bb0:
     %c0_i16 = hw.constant 0 : i16
+    // expected-error @+3 {{output type mismatch: output #0}}
+    // expected-note @+2 {{expected type: 'i32'}}
+    // expected-note @+1 {{actual type: 'i16'}}
     arc.output %c0_i16 : i16
   }
   hw.output
@@ -279,3 +302,20 @@ hw.module @memoryWritePortOpOutsideClockDomain(%en: i1) {
   // expected-error @+1 {{outside a clock domain requires a clock}}
   arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en : !arc.memory<4 x i32>, i32
 }
+
+// -----
+
+arc.define @outputOpVerifier () -> i32 {
+  // expected-error @+1 {{incorrect number of outputs: expected 1, but got 0}}
+  arc.output
+}
+
+// -----
+
+arc.define @outputOpVerifier () -> i32 {
+  %0 = hw.constant 0 : i16
+  // expected-error @+3 {{output type mismatch: output #0}}
+  // expected-note @+2 {{expected type: 'i32'}}
+  // expected-note @+1 {{actual type: 'i16'}}
+  arc.output %0 : i16
+}