[WireDFT] Add support for wiring optional clock div bypass signal. (#…

…5219) (#5225) If a signal is annotated as the clock divider bypass signal, wire it to clock gates that have the expected port. Like test_en wiring the port number is hardcoded, but unlike test_en this ignores the "bypass" port if that port doesn't match the expected bypass port name/dir/type. Warning is emitted if looks compatible but name doesn't match and bypass signal annotation is found.
llvm · May 18, 2023 · b1e3e33 · b1e3e33
1 parent 3e9e5fa
commit b1e3e33
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Showing 5 changed files with 335 additions and 152 deletions.
diff --git a/include/circt/Dialect/FIRRTL/AnnotationDetails.h b/include/circt/Dialect/FIRRTL/AnnotationDetails.h
@@ -91,6 +91,8 @@ constexpr const char *metadataDirectoryAttrName =
 constexpr const char *noDedupAnnoClass = "firrtl.transforms.NoDedupAnnotation";
 constexpr const char *dftTestModeEnableAnnoClass =
     "sifive.enterprise.firrtl.DFTTestModeEnableAnnotation";
+constexpr const char *dftClockDividerBypassAnnoClass =
+    "sifive.enterprise.firrtl.DFTClockDividerBypassAnnotation";
 
 // Grand Central Annotations
 constexpr const char *serializedViewAnnoClass =

diff --git a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp
@@ -468,6 +468,7 @@ static const llvm::StringMap<AnnoRecord> annotationRecords{{
     {extractAssumeAnnoClass, NoTargetAnnotation},
     {extractCoverageAnnoClass, NoTargetAnnotation},
     {dftTestModeEnableAnnoClass, {stdResolve, applyWithoutTarget<true>}},
+    {dftClockDividerBypassAnnoClass, {stdResolve, applyWithoutTarget<true>}},
     {runFIRRTLTransformAnnoClass, {noResolve, drop}},
     {mustDedupAnnoClass, NoTargetAnnotation},
     {addSeqMemPortAnnoClass, NoTargetAnnotation},