[NFC][FIRRTL] Canonicalize away empty probes (#6617)

llvm · Jan 27, 2024 · bab53e6 · bab53e6
1 parent 649ee55
commit bab53e6
Show file tree

Hide file tree

Showing 4 changed files with 52 additions and 0 deletions.
diff --git a/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td b/include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
@@ -86,6 +86,8 @@ def FPGAProbeIntrinsicOp : FIRRTLOp<"int.fpga_probe", []> {
   let arguments = (ins AnyType:$input, NonConstClockType:$clock);
   let results = (outs);
   let assemblyFormat = "$clock `,` $input attr-dict `:` type($input)";
+
+  let hasCanonicalizeMethod = 1;
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/lib/Dialect/FIRRTL/FIRRTLFolds.cpp b/lib/Dialect/FIRRTL/FIRRTLFolds.cpp
@@ -3289,3 +3289,34 @@ OpFoldResult HasBeenResetIntrinsicOp::fold(FoldAdaptor adaptor) {
 
   return {};
 }
+
+//===----------------------------------------------------------------------===//
+// FPGAProbeIntrinsicOp
+//===----------------------------------------------------------------------===//
+
+static bool isTypeEmpty(FIRRTLType type) {
+  return FIRRTLTypeSwitch<FIRRTLType, bool>(type)
+      .Case<FVectorType>(
+          [&](auto ty) -> bool { return isTypeEmpty(ty.getElementType()); })
+      .Case<BundleType>([&](auto ty) -> bool {
+        for (auto elem : ty.getElements())
+          if (!isTypeEmpty(elem.type))
+            return false;
+        return true;
+      })
+      .Case<IntType>([&](auto ty) { return ty.getWidth() == 0; })
+      .Default([](auto) -> bool { return false; });
+}
+
+LogicalResult FPGAProbeIntrinsicOp::canonicalize(FPGAProbeIntrinsicOp op,
+                                                 PatternRewriter &rewriter) {
+  auto firrtlTy = type_dyn_cast<FIRRTLType>(op.getInput().getType());
+  if (!firrtlTy)
+    return failure();
+
+  if (!isTypeEmpty(firrtlTy))
+    return failure();
+
+  rewriter.eraseOp(op);
+  return success();
+}
diff --git a/test/Dialect/FIRRTL/canonicalization.mlir b/test/Dialect/FIRRTL/canonicalization.mlir
@@ -3324,4 +3324,13 @@ firrtl.module @Whens(in %clock: !firrtl.clock, in %a: !firrtl.uint<1>, in %reset
   }
 }
 
+firrtl.module @Probes(in %clock: !firrtl.clock) {
+  // CHECK-NOT: firrtl.int.fpga_probe %clock, %zero_width : !firrtl.uint<0>
+  %zero_width = firrtl.wire : !firrtl.uint<0>
+  firrtl.int.fpga_probe %clock, %zero_width : !firrtl.uint<0>
+  // CHECK-NOT: firrtl.int.fpga_probe %clock, %empty_bundle : !firrtl.bundle<a: uint<0>>
+  %empty_bundle = firrtl.wire : !firrtl.bundle<a: uint<0>>
+  firrtl.int.fpga_probe %clock, %empty_bundle : !firrtl.bundle<a: uint<0>>
+}
+
 }
diff --git a/test/Dialect/FIRRTL/round-trip.mlir b/test/Dialect/FIRRTL/round-trip.mlir
@@ -23,6 +23,16 @@ firrtl.module @Intrinsics(in %ui : !firrtl.uint, in %clock: !firrtl.clock, in %u
   %cg1 = firrtl.int.clock_gate %clock, %ui1, %ui1
 }
 
+// CHECK-LABEL: firrtl.module @FPGAProbe
+firrtl.module @FPGAProbe(
+  in %clock: !firrtl.clock,
+  in %reset: !firrtl.uint<1>,
+  in %in: !firrtl.uint<8>
+) {
+  // CHECK: firrtl.int.fpga_probe %clock, %in : !firrtl.uint<8>
+  firrtl.int.fpga_probe %clock, %in : !firrtl.uint<8>
+}
+
 // CHECK-LABEL: firrtl.option @Platform
 firrtl.option @Platform {
   // CHECK:firrtl.option_case @FPGA