Firtool Release 1.26.0

Summary

• The tag name is renamed from sifive/ to firtool-
• Improved analog connection lowering
• A new combinatorial logic loop detection pass was merged
• Mux pragmas are stripped by default
• Extra guards to header macros
• SymbolDCE is moved to the later pipeline
• Bug fixes (IMCP invalid flow creation, ETC creates null operands)
• More aggregate preservation work

What's Changed

• Correct typos in ExpandWhens.cpp by @SpriteOvO in #4361
• [LowerXMR] Emit hierpathop's as private, so they can be removed if unused by @dtzSiFive in #4461
• [Scheduling] Overhaul simplex-based modulo scheduler. by @jopperm in #4426
• LLVM Bump by @nandor in #4463
• [LLHD] Install llhd-sim utility ### (when enabled). by @dtzSiFive in #4464
• [LowerToHW] Lower aggregate constant by @uenoku in #4451
• Revert "[LowerToHW] Lower aggregate constant" by @uenoku in #4465
• [FIRRTL] Simplify internal Analog connections by @tymcauley in #4466
• [FIRRTL] Fix InstanceOp Unknown Attribute Copying by @seldridge in #4468
• [CI] uploadBinaries.yml: Temporarily change 20.04 compiler to 12. by @dtzSiFive in #4475
• [CI] uploadBinaries: allow workflow_dispatch, test what we publish, drop cache by @dtzSiFive in #4474
• [NFC] small touchups before LLVM bump by @dtzSiFive in #4476
• [LowerToHW] Add extra guards to header macros by @uenoku in #4469
• [StandardToHandshake] Remove intermediate conversion ops by @RamirezLucas in #4480
• LLVM bump: move almost entirely to std::optional, fixes by @dtzSiFive in #4470
• [LowerSeqToSV] Initialize register element individually by @uenoku in #4478
• [ExportVerilog] Regard dead expressions as inlinable by @uenoku in #4486
• [SV] Mark SampledOp Pure by @uenoku in #4487
• [Seq] Create new clock enabled register op by @teqdruid in #4495
• [llvm] Bump LLVM to latest by @seldridge in #4491
• [PrepareForEmission] Handle twoState flags in variadic op lowerings by @uenoku in #4490
• [PyCDE] Improve Reg construct by @teqdruid in #4497
• [Pipeline] Add linear pipeline scheduling pass by @mortbopet in #4216
• [firtool] Strip mux pragmas by default, NFC by @uenoku in #4501
• [FIRRTL] remove GrandCentralSignalMapping pass + tests. by @dtzSiFive in #4505
• [firtool] Run SymbolDCE as late as possible. by @mikeurbach in #4504
• [FIRRTL] Handle Nodes in getDeclName. NFC. by @prithayan in #4512
• [FIRRTL][CheckCombCycles] Add a new pass to check for comb loops by @prithayan in #4368
• Bump LLVM by @youngar in #4511
• [LowerTypes] Force type lowering of ref type operations to fix memtap type mismatch by @uenoku in #4509
• [ExportVerilog] Inline bitcast op when only used by concat by @uenoku in #4493
• [Seq] Replace unitialized array elements of firreg with constant zero by @uenoku in #4510
• [CI] Enable statistics when building binaries for releases. by @dtzSiFive in #4515
• [FIRRTL][CheckCombLoops] Fix performance regression. by @prithayan in #4521
• [FIRRTL][CheckCombLoops] Switch to the new pass checkCombLoops instead of checkCombCycles by @prithayan in #4513

New Contributors

• @SpriteOvO made their first contribution in #4361

Full Changelog: sifive/1/25/0...firtool-1.26.0