Firtool Release 1.28.0

Summary

• Users can specify an include path to firtool using --include-dir <directory> as the long form of -I
• The FIRRTL parser no longer overrides port locations with module locations

What's Changed

• [FIRRTL] Use circuit location for annotation file parse errors. by @dtzSiFive in #4541
• [FIRRTL] Move FVectorType to ODS by @rwy7 in #4534
• [PyCDE] Add ControlReg construct by @teqdruid in #4536
• [FIRRTL] Move BundleType to ODS by @rwy7 in #4535
• [Python] Use the "private namespace" approach for mlir dep by @teqdruid in #4546
• [PyCDE][NFC] Hide the circt package in our namespace by @teqdruid in #4545
• [StandardToHandshake] Replace liveness analysis with SSA maximization by @RamirezLucas in #4520
• [PyCDE] Value -> Signal by @teqdruid in #4550
• [GC] Fail pass if emit errors about companion instantiation. by @dtzSiFive in #4552
• [FIRRTL] Mark DUT AddSeqMemPorts ports dontTouch by @seldridge in #4554
• [FIRRTL] Change FIRRTL fieldID fns to use uint64_t by @seldridge in #4528
• [CMake] Fix option CIRCT_LLHD_SIM_ENABLED by @SpriteOvO in #4555
• [FIRRTL] Move SIntType and UIntType to ODS by @rwy7 in #4529
• [PyCDE] Change module API to extend Module instead of using a decorator by @teqdruid in #4556
• [FIRRTL] Move enum attributes to dedicated td file by @rwy7 in #4562
• [SSP] Support OR-Tools-based schedulers in -ssp-schedule by @jopperm in #4525
• [Scheduling] Rewrite tests in SSP IR by @jopperm in #4523
• [Scheduling] Rewrite tests for OR-Tools-based schedulers in SSP IR by @jopperm in #4524
• [NFC] Document verilog baseline assumed for consuming tools by @darthscsi in #4575
• [Scheduling] Purge test passes. by @jopperm in #4572
• [firtool] Add --include-dir option, -I as alias. by @dtzSiFive in #4576
• [CI] Bump integration test images. by @jopperm in #4571
• [ExportVerilog] Move local name legalization to pre-pass by @uenoku in #4573
• [LowerTypes] Fix a race condition by @uenoku in #4582

Full Changelog: firtool-1.27.0...firtool-1.28.0