Firtool Release 1.32.0

Overview

• Implement an iterative Tarjan's SCC to detect cycles
• Fix insertion point for fieldID.
• Bump LLVM to top-of-tree
• Add a canonicalization to swap constant index and unknown index of array gets
• Tweak suggested release tags, suggest firtool over sifive.
• Handle all data-flow ops in FieldSource
• Make DUT module public
• Limit BitCast to passive output, fix non-passive input.
• Handle port dontTouch, add inner sym.
• Replace single-address memories with registers
• Propapate bin flags through icmp and variadic op canonicalizer
• Disable one folder for 25% end-to-end perf improvement.
• Fixups to avoid memory safety issues.
• Reduce dontTouch+zero-width error to warning.
• Improve MacOS published binaries and flow
• Allow wiring type-equivalent types.
• Add disallowArrayIndexInlining option
• Unshallow CIRCT clone in uploadBinaries workflow
• Use port locations for diagnostics, don't dump module.
• Add a workflow for building and uploading Python wheels.

What's Changed

• [CheckCombCycles] Implement an iterative Tarjan's SCC to detect cycles by @prithayan in #4642
• [ESI] Introduce pure_module.input and pure_module.output by @teqdruid in #4657
• [ESI] Lower pure modules into HW modules by @teqdruid in #4658
• [FIRRTL][LegacyWiring] Fix insertion point for fieldID. by @dtzSiFive in #4664
• Bump LLVM to top-of-tree by @seldridge in #4666
• [HW] Add a canonicalization to swap constant index and unknown index of array gets by @uenoku in #4668
• [cmake] Tweak suggested release tags, suggest firtool over sifive. by @dtzSiFive in #4676
• Handle all data-flow ops in FieldSource by @darthscsi in #4673
• silence warning by @darthscsi in #4678
• [LowerAnnotations] Make DUT module public by @uenoku in #4672
• Fix Combinational Component Builder by @andrewb1999 in #4680
• [FIRRTL] Limit BitCast to passive output, fix non-passive input. by @dtzSiFive in #4648
• [LowerToHW] Handle port dontTouch, add inner sym. by @dtzSiFive in #4675
• [MemOp] Replace single-address memories with registers by @nandor in #4687
• [ESI] [mostly NFC] Lower ports pass refactoring by @teqdruid in #4670
• [ESI] Initial FIFO signaling: read latency 0 style by @teqdruid in #4679
• [CombFolds] Propapate bin flags through icmp and variadic op canonicalizer by @uenoku in #4695
• [Arc] Add dialect by @fabianschuiki in #4681
• [Handshake] Fix incorrect operation deletion in EliminateCBranchIntoMux canonicalization pattern by @RamirezLucas in #4650
• [COMB] disable one folder for 25% end-to-end perf improvement. by @darthscsi in #4690
• [FIRRTL][FoldMemRegs] Fixups to avoid memory safety issues. by @dtzSiFive in #4702
• [LowerToHW] Reduce dontTouch+zero-width error to warning. by @dtzSiFive in #4703
• Improve MacOS published binaries and flow by @jackkoenig in #4701
• [LowerAnnotations] Allow wiring type-equivalent types. by @dtzSiFive in #4656
• [ExportVerilog] Add disallowArrayIndexInlining option by @fabianschuiki in #4706
• Unshallow CIRCT clone in uploadBinaries workflow by @jackkoenig in #4707
• [LowerToHW] Use port locations for diagnostics, don't dump module. by @dtzSiFive in #4708
• [PyCDE] Expose signaling and FIFO0 by @teqdruid in #4705
• [CI] Add a workflow for building and uploading Python wheels. by @mikeurbach in #4710
• [ESI] Add parameters to PureModule lowering by @teqdruid in #4711

Full Changelog: firtool-1.31.0...firtool-1.32.0