Firtool Release 1.33.0
Pre-release
Pre-release
EDIT: firtool 1.33.0 has a known issue in canonicalizers which causes a complication failure so please use firtool 1.34.0.
What's Changed
- [Arc] Add arc conversion pass by @fabianschuiki in #4697
- [FIRRTLFolds] Add a mux canonicalize pattern by @prithayan in #4720
- [ESI] Option to flatten struct messages by @teqdruid in #4712
- [PyCDE] Set dialect attributes on modules, expose flatten dialect attr by @teqdruid in #4723
- [ExportVerilog] More support for SV attributes by @uenoku in #4716
- LLVM bump by @dtzSiFive in #4704
- [FIRRTL][NFCI] Move RefType to ODS by @dtzSiFive in #4731
- Disable folder for 4734 by @darthscsi in #4735
- [Support] Move FirtoolPassInstrumentation to a support header, NFC by @uenoku in #4738
- [ExportVerilog] Lowering option to emit 'wire' in port list by @teqdruid in #4737
- [ESI] Add more flexibility to port names during lowering by @teqdruid in #4736
- [FIRRTL] Instrinsic Modules by @darthscsi in #4733
- [FIRRTL] Add a pass to convert VoB -> BoV conversion by @rwy7 in #4654
- [SV] Move emitAsComment to SVAttributeAttr; remove SVAttributesAttr by @fabianschuiki in #4743
- [ExportVerilog] Add KEEP attr to Vivado array index bug workaround by @fabianschuiki in #4744
- [CI] Swap build mode of gcc and clang by @uenoku in #4747
- [ExtractInstances] Fix nondeterminism by using MapVector. by @uenoku in #4749
Full Changelog: firtool-1.32.0...firtool-1.33.0