Firtool 1.57.0 Release
·
2117 commits
to main
since this release
What's Changed
- [FIRRTL][HoistPassthrough] Add pass to hoist must-driven output ports. by @dtzSiFive in #6115
- Remove GlobalRefOp, GlobalRefAttr by @seldridge in #6173
- [FIRRTL][DropConst] Mark InstanceGraph preserved. by @dtzSiFive in #6183
- [firtool] Add LowerGroups pass by @seldridge in #6182
- [FIRRTL][Hoist] Mark all analyses preserved if no changes. by @dtzSiFive in #6185
- [firtool] Deprecate -dedup option by @seldridge in #6188
- [Ibis] Allow tunneling from
hw.module
s by @mortbopet in #6195 - [Pipeline] Remove internal clock, reset,stall signals. by @mortbopet in #6196
- [Ibis] Print offending port name and use count on containers-to-hw error by @blakep-msft in #6186
- [FIRRTL][LOA] If no changes made, mark all analyses preserved. by @dtzSiFive in #6187
- [Ibis] Fix clean selfdrivers in case of external reads by @mortbopet in #6201
- [ExportVerilog] Format specifiers: hierpath separation character by @teqdruid in #6192
- [FIRRTL] Add GroupSink pass by @seldridge in #6184
- [FIRRTL] Cause "weak" OMIR Annotations to not block optimizations by @seldridge in #6200
- [Ibis] Fix issues in Tunneling and PortRef lowering by @mortbopet in #6202
- [Python] Use Ninja and LLD when building wheel if available by @uenoku in #6165
- [FIRRTL][RefSubOp] Add getAccessedField helper method. by @dtzSiFive in #6208
- [OM][Bindings] Make Python Evaluator Object hashable by @prithayan in #6204
- [ExportVerilog] Fix line count in debug verilog locations by @prithayan in #6210
- [FIRRTL] Simplify getFieldRefFromValue, add+use FieldRefCache. by @dtzSiFive in #6181
- Bump LLVM by @rwy7 in #6207
- llvm: Small bump to get version that passes tests. by @dtzSiFive in #6211
- [Seq][FirMemLowering] Create correct width constant for missing mask input by @prithayan in #6214
- [Ibis] Add ibistool by @mortbopet in #6206
- [Ibis] Reblock should also create blocks around non-delimited ops by @mortbopet in #6218
- [Ibis] Add
ibis-prepare-scheduling
pass by @mortbopet in #6166 - [FIRRTL][LOA][NFCI] Use FieldRefCache. by @dtzSiFive in #6215
- [FIRRTL] Bump FIRRTL version to 3.3.0 for parsing by @seldridge in #6217
- [Arc] Move LegalizeStateUpdate before StateAlloc by @zyedidia in #5830
- [HW] Change printer for modules by @darthscsi in #6205
- [MSFT] Remove Python extensions for non-existant structure ops. by @mikeurbach in #6221
- [ibis] Fix reblock use of erased ops by @seldridge in #6222
- [FIRRTL][Parser] Update groups version check to 3.2.0. by @dtzSiFive in #6219
- [Calyx] Add calyx.undef by @rachitnigam in #5964
- [HW] Disallow duplicate field names in HW aggregate types by @fzi-hielscher in #6225
- [Firtool][CAPI] Add C-API for Firtool lib by @SpriteOvO in #6036
- [Ibis] Add ibis.sblock.isolated by @mortbopet in #6230
- [OM] Implement PathAttr CAPI and Python binding by @uenoku in #6229
- [Ibis] Add handshake to DC conversion by @mortbopet in #6231
- [FIRRTL] Preserve port orders when lowering to HW. by @darthscsi in #6224
- [FIRRTL] Input probe support. by @dtzSiFive in #6121
- [ExportVerilog] Bound type size considered for decl alignment by @fabianschuiki in #6171
- [FirRegLowering] Implement refined check for mux-to-if conversion. by @mikeurbach in #6203
- [ESI] Lower bundles to channels by @teqdruid in #6216
- [Ibis] Add methods-to-containers pass by @mortbopet in #6232
- [Firtool] Rerun IMCP after register optimizations by @uenoku in #6179
- [FIRRTL][ExpandWhens] Support flow checking for local and remote objects by @rwy7 in #6212
- [Ibis] Added missing ibistool to integration test by @dobios in #6241
- [OM] Load post-export dialects in om-linker. by @mikeurbach in #6242
- [FIRRTL] Update LowerClasses to use the defname for ExtModules. by @mikeurbach in #6243
- [Arc] Add LowerArcsToFuncs pass by @zyedidia in #6227
- [ESI][Python] Expose BundleType to Python by @teqdruid in #6248
- [FIRRTL] Add canonicalizations for mux comparing its high and low operands by @trilorez in #6246
- [FIRRTLFolds] Remove InvalidValue canonicalization by @uenoku in #6080
- [Ibis] Add scheduling prototype by @mortbopet in #6239
- [Arc] Lower models into eval functions by @fabianschuiki in #6247
- [OM] Update FreezePaths to root paths at the nearest public module. by @mikeurbach in #6244
- [Debug] Add basic DebugInfo analysis and emission by @fabianschuiki in #6148
- [PyCDE] Fixing tests by @teqdruid in #6252
- [OM] Add more path types by @youngar in #6250
- [OM] Evaluator: Support graph regions by @uenoku in #6249
- [SV] Mark sv.xmr.ref op as pure by @fabianschuiki in #6260
- [FIRRTL][FIRParser] Prefer RWProbe op as much as possible. by @dtzSiFive in #5835
- [FIRRTL][MergeConnections] Reject non-passive aggregates. by @dtzSiFive in #6264
- [FIRRTL][NFC] Move FieldRef -> InnerSymTarget to utility. by @dtzSiFive in #6265
- [Seq] Add optional power-on value to
compreg
ops by @mortbopet in #6255 - [Seq][NFC] More flexible builders for compregs by @nandor in #6270
- [firtool] Add infra for pass plugins by @uenoku in #6254
- [Seq] Remove custom printer/parser for
seq.compreg(.ce)
ops by @mortbopet in #6267 - [PipelineToHW] Add optional power-on values to control registers by @mortbopet in #6269
- [Seq] Fix the canonicalization of seq registers with a clock type by @nandor in #6274
- [OM] Add location info to EvaluatorValue by @prithayan in #6240
- [FIRRTL][GrandCentral] Add a mode to drop companion modules by @nandor in #6268
- [circt-opt] Export symbols for MLIR plugins by @uenoku in #6278
- [CI] Install LLVM utils to release artifacts by @uenoku in #6279
- [OM] Overhaul of path operations by @youngar in #6253
- [Namespace] Return an empty string for empty string. by @uenoku in #6284
- [NFC] LLVM Bump by @trilorez in #6280
- [FIRRTL] Add strip option to DropName by @uenoku in #6281
- [LowerToHW] Fix symbol creation for empty names by @uenoku in #6282
- [ExtractTestCode] Specify non-empty unqiue port names by @prithayan in #6283
- Add emission for calyx std_signext by @rachitnigam in #6285
- [FIRRTL] Remove RecursiveMemoryEffects and RecursivelySpeculatable from When op, add canonicalizers by @uenoku in #6236
- [HW] round trip ModuleType non-ssa values by @darthscsi in #6287
New Contributors
Full Changelog: firtool-1.56.1...firtool-1.57.0