Firtool 1.60.0 Release
What's Changed
- [Arc] Fix InlineArcs pass performance by @maerhart in #6379
- [ExportVerilog] Make ExprEmitter sensitive to assignment-like context by @fabianschuiki in #6329
- [HW] Verify dimensions for hw.aggregate_constant ops by @fzi-hielscher in #6380
- [ESI][Runtime] Read a manifest and build the design hierarchy by @teqdruid in #6384
- [CI] Update Python wheel action for MacOS. by @mikeurbach in #6386
- [FIRRTL] Simplify muxes when a particular bit value selects the same value. by @darthscsi in #6382
- [Docs] Fixed typo in VerilogGeneration.md by @dobios in #6394
- [Docs] Fix documentation typos, NFC by @tymcauley in #6393
- [ESI][Runtime] Create a 'trace' accelerator backend by @teqdruid in #6396
- [Seq] Add the
Clocked
trait to FIR mem read/write ops by @nandor in #6401 - [ESI][Runtime] Start of types by @teqdruid in #6397
- [OM] Tweak PathAttr syntax to be more amenable to bytecode. by @mikeurbach in #6403
- [OM] Remove enum type. by @mikeurbach in #6408
- [FIRRTL] Remove Map property type and expressions. by @mikeurbach in #6407
- [HWLegalizeModules] Lower types-like packed array handling (#5355) by @yupferris in #6402
- [ESI][Runtime] Wire up services and ports into the design tree by @teqdruid in #6406
- [ESI][Runtime][NFC] Cleanup runtime code by @teqdruid in #6411
- [Seq] Move the HWMemSimImpl pass to seq by @nandor in #6409
- [Seq] Add shiftreg op by @mortbopet in #6038
- [Comb] Disallow canonicalization across MLIR blocks by @mortbopet in #6235
- [FIRRTL] Add GroupMerge pass by @seldridge in #6412
- [FIRRTL][CAPI] Add functions for property types by @SpriteOvO in #6413
- [HWMemSimImpl] Add a mode to set disabled outputs to zero by @nandor in #6414
- Bump LLVM by @girishpai in #6404
- [HW] Fix bug with unknown location by @leonardt in #6416
- [HW] Move getPortVerilogName helper into HW PortInfo; NFC by @fabianschuiki in #6421
- [firtool] Remove -dedup option by @seldridge in #6191
- [Debug] Add expression support to HGLDD emission by @fabianschuiki in #6334
- [Firtool][CAPI] Remove dedup option from C API by @fzi-hielscher in #6423
- [FIRRTL][OM] Rebase path operations throughout the module hierarchy by @youngar in #6420
- [Seq] Move register & memory macro headers to SeqToSV by @nandor in #6419
- Bump LLVM by @uenoku in #6424
- [FIRRTL][LowerType] Handle unrealized_conversion_cast of other dialects by @prithayan in #6422
- [ESI] Cosim: punt endpoint naming to users by @teqdruid in #6427
- [ESI][Runtime] Add cosimulation support to new runtime by @teqdruid in #6428
- [ESI][Runtime] Access children and ports by name by @teqdruid in #6429
- [PyCDE] Fixing everything unexpectedly broken by @teqdruid in #6430
- [ESI][Runtime] Make GCC happy too by @teqdruid in #6431
- [LowerToHW] Pass through attributes on FModuleOp by @uenoku in #6400
- [FIRRTL] Verify public FModuleLike's don't have input probes. by @dtzSiFive in #6434
- [InstanceGraph] Remove the module lookup helper by @nandor in #6425
- [Comb]: Canonicalize and(x,y) and or(x,y) when x and y are defined by opposite comparisons by @devins2518 in #6374
- [ESI] Fix AppID index walk by @teqdruid in #6442
- [FIRRTL] Internally Rename "Groups" to "Layers" by @seldridge in #6443
- [FIRRTLFolds] Fix FoldZeroWidthMemory to write zero for zero bit wire by @uenoku in #6238
- [InferResets] Transition the pass to use the InstancePathCache by @nandor in #6440
- [HWMemSimImpl] Set visibility of generated modules private by @uenoku in #6444
- [FIRTOOL] Make firtool options behave like the rest of llvm. by @darthscsi in #6435
- [PyCDE] Use bundles for ESI services by @teqdruid in #6436
- [HW] Introduce the
hw.instance_choice
op by @nandor in #6447 - [ESI] Move Cosim manifest into separate module by @teqdruid in #6456
- [HW][FlattenIO] Fix extern module instances by @prithayan in #6441
- [ExportVerilog] Skip debug dialect ops by @fabianschuiki in #6453
- [firrtl] Add 4.0.0 public modules by @seldridge in #6448
- [ESI] Enable i0 sends and recvs over cosim by @teqdruid in #6459
- [ESI][Manifest] Make service records required by @teqdruid in #6461
- [ESI][Runtime] When a service cannot be created, ignore it by @teqdruid in #6462
- [PyCDE] Fixing integration tests by @teqdruid in #6463
- Add lowering for ILA Probe Intrinsic by @adkian-sifive in #6415
New Contributors
- @yupferris made their first contribution in #6402
Full Changelog: firtool-1.59.0...firtool-1.60.0