SiFive Internal Release 1.23.0

Overview

• IMDCE to eliminate dead memories
• Grand Central wire2node change
• Namehint propagation improvement
• A flag to workaround vivado BRAM inference bug
• Refactor FIRRTL canonicalizers to use ODS patterns

What's Changed

• [IMDCE] Allow dead memories to be eliminated by @nandor in #4244
• Add options for controlling emission of randomization code. by @dtzSiFive in #4240
• [FIRRTL] Cleanup GCT Views Tests to RefType, NFC by @seldridge in #4247
• [docs][Seq] Fixup seq.firreg documentation to reflect current op. by @dtzSiFive in #4250
• [FIRRTL][LowerXMR] Copy DenseMap to temporary before insertion by @prithayan in #4243
• [Docs] Fix typo in pass description by @tymcauley in #4248
• [FIRRTL][MemOp] Removed unused ports from memories by @nandor in #4242
• [SSP] Extract helper to access linked operator type, NFC. by @jopperm in #4258
• [FIRRTL][LowerXMR] Use InstanceGraph to get referencedModule by @prithayan in #4254
• [NFC] verilog-basic.mlir: Fix duplicate definition of symbol in test case. by @dtzSiFive in #4268
• Fix bug in memory canonicalizer when all ports are unused. Make patterns named to make debugging easier. by @darthscsi in #4265
• [DropNames] Reuse a droppable name attribute, nfc by @uenoku in #4259
• [LowerToHW] Fix the operand order of VectorCreateOp lowering by @uenoku in #4260
• [ExportVerilog] Fix port spacing on instances, measure emitted name. by @dtzSiFive in #4264
• Remove invalids from canonicalizers. They are always wrong. by @darthscsi in #4271
• [FIRRTL] Convert Wires To Nodes when dominance allows by @darthscsi in #4253
• [FIRRTL] Remove Annotation-style GCT Views by @seldridge in #4251
• [LowerSeqToSV] Self-assign of Async Reset FIR Reg by @seldridge in #4273
• [SV][Prepare] Improve a namehint propagation and spilling logic by @uenoku in #4261
• [Docs] Fix typo in FIRRTL Types description by @tymcauley in #4276
• Bump LLVM by @youngar in #4262
• [FIRRTL] Fix RegResetWithOneReset Canonicalizer by @seldridge in #4279
• [Handshake] Canonicalize away simple mux+cbranch structures by @RamirezLucas in #4272
• [FIRRTL] Guarantee NodeOp in GCT View by @seldridge in #4278
• [Handshake] Fix ValueRange lifetime issue. by @dtzSiFive in #4283
• [FIRRTL][Dedup] Fix cloning annotations for more context by @youngar in #4285
• Make flatten memory pass default. Create lower-memory flag. by @carlosedp in #4275
• [LowerToHW] Support 1d vector aggregate constant by @uenoku in #4280
• [Python] Register handshake passes by @teqdruid in #4290
• [RTL-SIM] Fix trace debug output in Verilator driver by @teqdruid in #4293
• [ESI] Move ESI collateral into build include directory by @teqdruid in #4292
• [SSP] Allow standalone use of OperatorLibraryOp. by @jopperm in #4222
• [ESI] Support BSPs in service metadata emission by @teqdruid in #4299
• [tools] Change tools to use CIRCT-specific bug msg by @seldridge in #4302
• [HW][Seq] Added traits to identify clocked and resettable elements by @nandor in #4294
• [FIRRTL] Add WiringProblem Solver to LowerAnnotations, use for GrandCentral Views by @seldridge in #4286
• Bump LLVM by @prithayan in #4297
• [FIRRTL] Remove Grand Central Parent Annotation by @seldridge in #4305
• [SV] Update SVExtractTestCode to handle already bound instances. by @mikeurbach in #4291
• [Seq] Use a new pass generation mechanism by @uenoku in #4304
• [SSP] Define ChainingProblem's properties. by @jopperm in #4220
• [FIRRTL] Move DShift to patterns by @darthscsi in #4308
• [CI] Swap static and shared library by @uenoku in #4310
• [FIRRTL] Preserve names on expressions when applying canonicalization patterns by @darthscsi in #4307
• [NFC] Move connect canonicalization to patterns by @darthscsi in #4306
• [FIRRTL] Eliminate more invalid canonicalization by @darthscsi in #4314
• [LowerToHW] Lower i0 operand in printf-encoded assertions to i1 by @uenoku in #4311
• [docs][NFC] Fix dead chisel-lang API links "temporarily". by @dtzSiFive in #4313
• [FIRRTL] Move more canonicalizations to patterns. by @darthscsi in #4316
• [FIRRTL] Change Wires to Nodes in WiringProblems by @seldridge in #4312
• Revert "[FIRRTL] Convert Wires To Nodes when dominance allows (#4253)" by @uenoku in #4317
• [LowerAnnotations][WiringProblem] minor reorg, debug print all problems. by @dtzSiFive in #4322
• [GrandCentralTaps] Move (new) MemTaps to WiringProblem. by @dtzSiFive in #4320
• [Docs] Add SSP to dialect diagram. by @jopperm in #4295
• [SV] Verify that sv.interface.instance ops have a nonempty name by @rwy7 in #4315
• [HWMemSim, LowerSeqToSV] Add a flag to annotate array registers with (*ram_style = "distributed" *) by @uenoku in #4288
• [FIRRTL] Require MultibitMuxOp Index is Unsigned by @seldridge in #4325
• [FIRRTL][CheckCombCycles] Detect input port self loops by @prithayan in #4330
• [Handshake][lit] Move buff insertion tests to correct dir by @Dinistro in #4329
• llvm-bump by @Ramlakshmi3733 in #4321

New Contributors

• @RamirezLucas made their first contribution in #4272
• @carlosedp made their first contribution in #4275
• @rwy7 made their first contribution in #4315
• @Ramlakshmi3733 made their first contribution in #4321

Full Changelog: sifive/1/22/0...sifive/1/23/0