SiFive Internal Release 1.24.0

What's Changed

• [HWArith] Support signedness values inside sv wire/reg/read_inout by @mortbopet in #4331
• [Scheduling][SSP] Restore feature parity between infra and dialect. by @jopperm in #4333
• [GrandCentralTaps] Move data taps to WiringProblem. by @dtzSiFive in #4323
• [ExportVerilog] Use pretty-printer for improved output formatting. by @dtzSiFive in #4194
• [HW] Add pass for flattening structs in module in/out ports by @mortbopet in #4007
• [PyCDE] Support for BSP-defined packaging by @teqdruid in #4338
• [PyCDE] NamedWire construct by @teqdruid in #4337
• [FIRRTL] Remove ScalaClassAnnotation after consuming it. by @mikeurbach in #4346
• [GrandCentral] Ignore deduped Companion views by @prithayan in #4309
• [StandardToHandshake] Cleanup std to handshake tests by @Dinistro in #4336
• [FIRRTL] Improve folding of ports by @nandor in #4289
• [FIRRTL][GrandCentral] Fix mem corruption by @prithayan in #4351
• [FIRRTL] Reject string literals with non-7bit-ASCII or {u,U}. by @dtzSiFive in #4345
• [FIRRTL][GrandCentralTaps] Don't add NoDedup annotation to Tap sinks by @prithayan in #4347
• [SV][ExportVerilog] Add XMRRefOp, Add ExportVerilog Emissions by @seldridge in #4349
• [Handshake] Fix use-after-free bugs in canonicalization patterns. by @richardxia in #4355
• [FIRRTL] Add Inner Symbol DCE Pass by @seldridge in #3120
• [IMDCE] Generate warnings if empty modules are kept by @uenoku in #4350
• Fix error in reducer test for annotation-remover by @rwy7 in #4356
• [FIRRTL] Don't match invalids with getConstant by @darthscsi in #4319
• [HW] Move Firrtl's innersym attribute to hw by @darthscsi in #4360
• [FIRRTL] Use nested array for aggregate constants by @darthscsi in #4348
• [SSP] Set up pass boilerplate. by @jopperm in #4363
• [PrepareForEmission] Remove unnecessary tempoary introduced by bitcast op by @uenoku in #4366
• [Python] Fix path to python when it has spaces by @teqdruid in #4371
• [SSP] Add -ssp-schedule pass with initial support for the simplex schedulers. by @jopperm in #4364
• [SSP] Rename DOT printer pass, NFC. by @jopperm in #4372
• Bump llvm 2022-11-22 by @richardxia in #4353
• [SSP] Add pass to roundtrip via the scheduling infra. by @jopperm in #4373
• [FIRRTL][IMCP] Mark aggregate as overdefined by @uenoku in #4370
• [hlstool] Move extmem lowering in pass pipeline by @mortbopet in #4376
• [GrandCentral] Fix insertion point for external module source by @dtzSiFive in #4377
• [FIRRTL] Extend some constant folds. by @darthscsi in #4379
• [FIRRTL][LowerXMR] Ignore 0-width RefType values by @prithayan in #4380
• [PyCDE] PyTorch (dot product) integration test by @teqdruid in #4352
• [Scheduling] Calculate resII before solving ModuloProblem by @matth2k in #4374
• [MergeConnections] Use vector/bundle create and enable aggressive merging by default by @uenoku in #4385
• [GCT][LowerAnnos] Use no-op cast to avoid erasing sources. by @dtzSiFive in #4390
• [ExportVerilog] Sink mux inlining check to isExpressionEmittedInline. by @mikeurbach in #4392
• [CombFolds] Handle array operations in flattenConcat by @uenoku in #4389
• [FIRRTL] Fold binary ops returning zero-width, replace impossible check. by @dtzSiFive in #4395
• [GCSM] Fix buffer wire preservation, add test. by @dtzSiFive in #4397
• [COMB] Factor Mux of Mux with common child conditions and common child values by @darthscsi in #4403
• [COMB] mux of muxes with identical branches can be simplified by @darthscsi in #4405

New Contributors

• @matth2k made their first contribution in #4374

Full Changelog: sifive/1/23/0...sifive/1/24/0