SiFive Internal Release 1.25.0

Overview

• Grand Central Views will now have ports on their companion module, as part of ongoing work to enable their deduplication.
• Intrinsics support, via annotated external modules as not yet part of FIRRTL language.
• New AggregateConstantOp
• Support for printf-encoded cover statements
• FIRRTL parser no longer rejects zero-width literals
• EmitOMIR support for fields
• Minor PrettyPrinter formatting tweaks: braced lists, allow indenting past target line width when needed
• Canonicalizer/folding improvements
• IMDCE and IMCP improvements
• Many improvements to XMR, Wiring, and unifying InnerSymbol/InnerRef infrastructure

What's Changed

• Register FIRRTL to CAPI by @sequencer in #4404
• unittests: Squelch -Wsuggest-override errors in LLVM's gtest. by @dtzSiFive in #4409
• [ExportVerilog] Tweak braced list formatting, less whitespace. by @dtzSiFive in #4406
• [PyCDE] Ok that out dirs may already exist by @mortbopet in #4415
• [IMDCE] Improve liveness propagation of input ports by @uenoku in #4410
• [PrettyPrinter] Enable maxStartingIndent feature, default to high value. by @dtzSiFive in #4408
• [EmitOMIR] Support fieldID for OMIR targetting fields. by @mikeurbach in #4407
• Bump LLVM to f6b1d88527886683a67bebf27df3ad626fa3940e. by @mikeurbach in #4420
• [Handshake] Cleanup Handshake operations builders by @RamirezLucas in #4416
• [HW] Add constant aggregate op by @youngar in #4402
• [hlstool] Remove header to fix flaky build by @youngar in #4427
• [FIRRTL] Update subfield format by @rwy7 in #4430
• [FIRRTL] Add support for "intrinsics" by @darthscsi in #4429
• Bump llvm by @uenoku in #4432
• [FIRRTL] Support for cover statements by @debs-sifive in #4393
• [NFC] Disable -Wno-suggest-override for llvm_gtest_main as well. by @dtzSiFive in #4434
• [StandardToHandshake] Take fork/sink materialization out of conversion pass by @RamirezLucas in #4431
• [PyCDE] Wire construct improvements by @teqdruid in #4435
• Bump LLVM to 53406427cdf4290986d1a48ea0d582ad195bff15. by @mikeurbach in #4436
• [FIRRTL][HW] Move getNumPorts to HWModuleLike by @seldridge in #4394
• [CI] Bump integration test images by @teqdruid in #4441
• [Doumentation][PyCDE] Update PyCDE.md 'Manual Compile' section by @karakagi in #4433
• [HW][ExportVerilog] Use HierPathOp in XMRRefOp by @seldridge in #4421
• [FIRRTL] Change LowerXMR to create XMRRefOps by @seldridge in #4422
• [FIRRTL][IMCP] Lower unconnected registers to invalids by @darthscsi in #4445
• [FIRRTL] Support zero-width literals. by @dtzSiFive in #4440
• [WireDFT] harden a bit, check clock gate modules. by @dtzSiFive in #4449
• [SV] String types and system functions by @darthscsi in #4450
• [FIRRTL][GrandCentralTaps] Handle sink subfield for internal path by @prithayan in #4455
• [.github] Use ubuntu-latest in assign-reviewers CI by @seldridge in #4457
• [FIRRTL] Don't insert same-width pad for connect -> strictconnect. by @dtzSiFive in #4459
• [FIRRTL] Fix folding cat(SInt<0>,x), return needs to be unsigned. by @dtzSiFive in #4458
• [FIRRTL] Bore real input ports in WiringProblems by @seldridge in #4340
• Bump LLVM to afb2ed80cb1639236a3aa15f2c9ff96dbb45c3d0. by @mikeurbach in #4444

New Contributors

• @debs-sifive made their first contribution in #4393
• @karakagi made their first contribution in #4433

Full Changelog: sifive/1/24/0...sifive/1/25/0