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SiFive Internal Release 1.6.0

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@youngar youngar released this 29 Jun 03:58
· 5087 commits to main since this release
sifive/1/6/0
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Learn about vigilant mode.

What's Changed

  • [ExportVerilog] Add option to not emit location info by @rsetaluri in #3409
  • [PrepareForEmission] Add a pass to run only PrepareForEmission by @uenoku in #3371
  • Treat regreset the same in its initial lattice value as reg by @darthscsi in #3392
  • Bump LLVM to cb69ba4faaf1de207b363b5198d33e29d0375e5d. by @richardxia in #3386
  • Allow arbitrary order of idempotent or operations by @Schottkyc137 in #3416
  • [FSM] Remove SingleBlockImplicitTerminator from StateOp, TransitionOp by @mortbopet in #3405
  • [PyCDE,CAPI] Add support for the FSM dialect by @mortbopet in #3400
  • [FIRRTL] Move the getInnerRefTo to a Utility by @prithayan in #3408
  • [MSFT] AppID attribute by @teqdruid in #3425
  • [FIRRTL] InnerSymbolTable: move to own header, add helpers by @dtzSiFive in #3407
  • [SV] Add sv.attributes support to assign op by @uenoku in #3422
  • [MSFT] Pass to discover AppIDs by @teqdruid in #3426
  • [FIRRTL][GCSM] Use buffer wires for forced output ports by @youngar in #3431
  • [FIRRTL] AnnotationDetails.h: be consistent, prefer constexpr [NFC] by @dtzSiFive in #3432

New Contributors

Full Changelog: sifive/1/5/1...sifive/1/6/0

Contributors

richardxia, teqdruid, and 8 other contributors
Assets 3
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