More?

Author: AZero13

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -10019,7 +10019,8 @@ SDValue DAGCombiner::visitShiftByConstant(SDNode *N) {
                             BinOpLHSVal.getOpcode() == ISD::SRL) &&
                            isa<ConstantSDNode>(BinOpLHSVal.getOperand(1));
   bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg ||
-                        BinOpLHSVal.getOpcode() == ISD::SELECT;
+                        BinOpLHSVal.getOpcode() == ISD::SELECT ||
+                        BinOpLHSVal.getOpcode() == ISD::VSELECT;
 
   if (!IsShiftByConstant && !IsCopyOrSelect)
     return SDValue();
@@ -13437,7 +13438,7 @@ static SDValue tryToFoldExtendOfConstant(SDNode *N, const SDLoc &DL,
   // fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
   // fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2)
   // fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
-  if (N0->getOpcode() == ISD::SELECT) {
+  if (N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) {
     SDValue Op1 = N0->getOperand(1);
     SDValue Op2 = N0->getOperand(2);
     if (isa<ConstantSDNode>(Op1) && isa<ConstantSDNode>(Op2) &&
@@ -17765,10 +17766,11 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
   // fold (fmul X, (select (fcmp X > 0.0), -1.0, 1.0)) -> (fneg (fabs X))
   // fold (fmul X, (select (fcmp X > 0.0), 1.0, -1.0)) -> (fabs X)
   if (Flags.hasNoNaNs() && Flags.hasNoSignedZeros() &&
-      (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
+      (N0.getOpcode() == ISD::SELECT || N0.getOpcode() == ISD::VSELECT ||
+       N1.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::VSELECT) &&
       TLI.isOperationLegal(ISD::FABS, VT)) {
     SDValue Select = N0, X = N1;
-    if (Select.getOpcode() != ISD::SELECT)
+    if (Select.getOpcode() != ISD::SELECT && Select.getOpcode() != ISD::VSELECT)
       std::swap(Select, X);
 
     SDValue Cond = Select.getOperand(0);