[llvm-exegesis][RISCV] computeAliasingInstructions in SerialSnipperGenerate generates instructions that can't be assembled

[topperc]

I tried to run through all RISC-V opcodes available on my SiFive P550 system using -opcode-index=-1. I got some crashes trying to assemble pseudo instructions.

Should llvm-exegesis be filtering pseudos and custom insertion instructions in this function?

CC: @boomanaiden154 @mshockwave

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Craig Topper (topperc)

I tried to run through all RISC-V opcodes available on my SiFive P550 system using -opcode-index=-1. I got some crashes trying to assemble pseudo instructions.

Should llvm-exegesis be filtering pseudos and custom insertion instructions in this function?

CC: @boomanaiden154 @mshockwave

[llvmbot]

@llvm/issue-subscribers-tools-llvm-exegesis

Author: Craig Topper (topperc)

I tried to run through all RISC-V opcodes available on my SiFive P550 system using -opcode-index=-1. I got some crashes trying to assemble pseudo instructions.

Should llvm-exegesis be filtering pseudos and custom insertion instructions in this function?

CC: @boomanaiden154 @mshockwave

[boomanaiden154]

Probably. llvm/tools/llvm-exegesis/lib/X86/Target.cpp excludes a bunch of opcodes for various reasons, mostly a lack of support for benchmarking with memory I think. Given benchmarking pseudo instructions is probably not super meaningful, just excluding them probably makes the most sense.

[topperc]

Probably. llvm/tools/llvm-exegesis/lib/X86/Target.cpp excludes a bunch of opcodes for various reasons, mostly a lack of support for benchmarking with memory I think. Given benchmarking pseudo instructions is probably not super meaningful, just excluding them probably makes the most sense.

Is that this code and the isInvalidOpcode function?

  bool allowAsBackToBack(const Instruction &Instr) const override {              
    const unsigned Opcode = Instr.Description.Opcode;                            
    return !isInvalidOpcode(Instr) && Opcode != X86::LEA64r &&                   
           Opcode != X86::LEA64_32r && Opcode != X86::LEA16r;                    
  }