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[X86] Manage atomic load of fp -> int promotion in DAG #120386

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[X86] Manage atomic load of fp -> int promotion in DAG #120386

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[X86] Manage atomic load of fp -> int promotion in DAG
jofrn Dec 18, 2024
259109a
Update llvm/test/CodeGen/X86/atomic-load-store.ll
arsenm Mar 4, 2025
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4 changes: 4 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2647,6 +2647,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}

setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);

// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
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37 changes: 37 additions & 0 deletions llvm/test/CodeGen/X86/atomic-load-store.ll
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Expand Up @@ -145,3 +145,40 @@ define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind {
%ret = load atomic <1 x i64>, ptr %x acquire, align 8
ret <1 x i64> %ret
}

define <1 x half> @atomic_vec1_half(ptr %x) {
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Add the bfloat test

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1 x bfloat is added here: https://github.com/llvm/llvm-project/pull/120385/files.

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I'm not sure why bfloat is special such that it needs to be split out

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Just handle bfloat here like the rest? tt

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It is already scalarized from a v1bf16 to an i16. It doesn't require setting setOperationPromotedToType to lower in the same way.

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@arsenm arsenm Jan 7, 2025 •
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So it is still testable here. Plus is it legal on some subtarget? That would need to be tested and will go down a different path

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I’m testing it at the commit that enables it at the moment. It is easy to move it to this one.

; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
; CHECK3-NEXT: movzwl (%rdi), %eax
; CHECK3-NEXT: pinsrw $0, %eax, %xmm0
; CHECK3-NEXT: retq
;
; CHECK0-LABEL: atomic_vec1_half:
; CHECK0: ## %bb.0:
; CHECK0-NEXT: movw (%rdi), %cx
; CHECK0-NEXT: ## implicit-def: $eax
; CHECK0-NEXT: movw %cx, %ax
; CHECK0-NEXT: ## implicit-def: $xmm0
; CHECK0-NEXT: pinsrw $0, %eax, %xmm0
; CHECK0-NEXT: retq
%ret = load atomic <1 x half>, ptr %x acquire, align 2
ret <1 x half> %ret
}

define <1 x float> @atomic_vec1_float(ptr %x) {
; CHECK-LABEL: atomic_vec1_float:
; CHECK: ## %bb.0:
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: retq
%ret = load atomic <1 x float>, ptr %x acquire, align 4
ret <1 x float> %ret
}

define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
; CHECK-LABEL: atomic_vec1_double:
; CHECK: ## %bb.0:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: retq
%ret = load atomic <1 x double>, ptr %x acquire, align 8
ret <1 x double> %ret
}