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[RISCV] Allocate feature bits for Zifencei and Zmmul #143306

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[RISCV] Allocate feature bits for Zifencei and Zmmul #143306

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4 changes: 4 additions & 0 deletions compiler-rt/lib/builtins/cpu_model/riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -134,6 +134,10 @@ struct {
#define ZCLSD_BITMASK (1ULL << 9)
#define ZCMP_GROUPID 1
#define ZCMP_BITMASK (1ULL << 10)
#define ZIFENCEI_GROUPID 1
#define ZIFENCEI_BITMASK (1ULL << 11)
#define ZMMUL_GROUPID 1
#define ZMMUL_BITMASK (1ULL << 12)

#if defined(__linux__)

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6 changes: 4 additions & 2 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -134,7 +134,8 @@ def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
"(Integer Conditional Operations)">;

def FeatureStdExtZifencei
: RISCVExtension<2, 0, "fence.i">;
: RISCVExtension<2, 0, "fence.i">,
RISCVExtensionBitmask<1, 11>;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
Expand Down Expand Up @@ -192,7 +193,8 @@ def NoHasStdExtZilsd : Predicate<"!Subtarget->hasStdExtZilsd()">;
// Multiply Extensions

def FeatureStdExtZmmul
: RISCVExtension<1, 0, "Integer Multiplication">;
: RISCVExtension<1, 0, "Integer Multiplication">,
RISCVExtensionBitmask<1, 12>;
def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
AssemblerPredicate<(all_of FeatureStdExtZmmul),
"'Zmmul' (Integer Multiplication)">;
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