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[RISCV][llvm] Support logical comparison codegen for P extension #174626

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[RISCV][llvm] Support logical comparison codegen for P extension #174626

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7fd88eb
[RISCV][llvm] Support logical comparison codegen for P extension
4vtomat Jan 6, 2026
ebdfb3c
fixup! reorder pattern
4vtomat Jan 7, 2026
29f2fbe
Merge remote-tracking branch 'origin/main' into p_ext_codegen_compare
4vtomat Jan 8, 2026
d5d3d7f
fixup! leave only beq, blt and bltu pattern
4vtomat Jan 8, 2026
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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -546,6 +546,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SHL, ISD::SRL, ISD::SRA}, VTs, Custom);
setOperationAction(ISD::BITCAST, VTs, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VTs, Custom);
setOperationAction(ISD::SETCC, VTs, Legal);
// P extension vector comparisons produce all 1s for true, all 0s for false
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
}

if (Subtarget.hasStdExtZfbfmin()) {
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76 changes: 76 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoP.td
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Expand Up @@ -1584,6 +1584,54 @@ let Predicates = [HasStdExtP] in {
// // splat pattern
def: Pat<(XLenVecI8VT (splat_vector (XLenVT GPR:$rs2))), (PADD_BS (XLenVT X0), GPR:$rs2)>;
def: Pat<(XLenVecI16VT (splat_vector (XLenVT GPR:$rs2))), (PADD_HS (XLenVT X0), GPR:$rs2)>;

// 8/16-bit comparison patterns (result is all 1s or all 0s per element)
// a == b
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs1), (XLenVecI8VT GPR:$rs2), SETEQ)),
(PMSEQ_B GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs1), (XLenVecI16VT GPR:$rs2), SETEQ)),
(PMSEQ_H GPR:$rs1, GPR:$rs2)>;
// a != b => !(a == b)
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs1), (XLenVecI8VT GPR:$rs2), SETNE)),
(XORI (PMSEQ_B GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs1), (XLenVecI16VT GPR:$rs2), SETNE)),
(XORI (PMSEQ_H GPR:$rs1, GPR:$rs2), -1)>;
// a < b
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs1), (XLenVecI8VT GPR:$rs2), SETLT)),
(PMSLT_B GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs1), (XLenVecI8VT GPR:$rs2), SETULT)),
(PMSLTU_B GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs1), (XLenVecI16VT GPR:$rs2), SETLT)),
(PMSLT_H GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs1), (XLenVecI16VT GPR:$rs2), SETULT)),
(PMSLTU_H GPR:$rs1, GPR:$rs2)>;
// a <= b => !(b < a)
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs2), (XLenVecI8VT GPR:$rs1), SETLE)),
(XORI (PMSLT_B GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs2), (XLenVecI8VT GPR:$rs1), SETULE)),
(XORI (PMSLTU_B GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs2), (XLenVecI16VT GPR:$rs1), SETLE)),
(XORI (PMSLT_H GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs2), (XLenVecI16VT GPR:$rs1), SETULE)),
(XORI (PMSLTU_H GPR:$rs1, GPR:$rs2), -1)>;
// a > b => b < a
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs2), (XLenVecI8VT GPR:$rs1), SETGT)),
(PMSLT_B GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs2), (XLenVecI8VT GPR:$rs1), SETUGT)),
(PMSLTU_B GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs2), (XLenVecI16VT GPR:$rs1), SETGT)),
(PMSLT_H GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs2), (XLenVecI16VT GPR:$rs1), SETUGT)),
(PMSLTU_H GPR:$rs1, GPR:$rs2)>;
// a >= b => !(a < b)
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs1), (XLenVecI8VT GPR:$rs2), SETGE)),
(XORI (PMSLT_B GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(XLenVecI8VT (setcc (XLenVecI8VT GPR:$rs1), (XLenVecI8VT GPR:$rs2), SETUGE)),
(XORI (PMSLTU_B GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs1), (XLenVecI16VT GPR:$rs2), SETGE)),
(XORI (PMSLT_H GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(XLenVecI16VT (setcc (XLenVecI16VT GPR:$rs1), (XLenVecI16VT GPR:$rs2), SETUGE)),
(XORI (PMSLTU_H GPR:$rs1, GPR:$rs2), -1)>;
} // Predicates = [HasStdExtP]

let Predicates = [HasStdExtP, IsRV32] in {
Expand Down Expand Up @@ -1643,6 +1691,34 @@ let Predicates = [HasStdExtP, IsRV64] in {
// splat pattern
def: Pat<(v2i32 (splat_vector (XLenVT GPR:$rs2))), (PADD_WS (XLenVT X0), GPR:$rs2)>;

// 32-bit comparison patterns (result is all 1s or all 0s per element)
// a == b
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs1), (v2i32 GPR:$rs2), SETEQ)),
(PMSEQ_W GPR:$rs1, GPR:$rs2)>;
// a != b => !(a == b)
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs1), (v2i32 GPR:$rs2), SETNE)),
(XORI (PMSEQ_W GPR:$rs1, GPR:$rs2), -1)>;
// a < b
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs1), (v2i32 GPR:$rs2), SETLT)),
(PMSLT_W GPR:$rs1, GPR:$rs2)>;
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs1), (v2i32 GPR:$rs2), SETULT)),
(PMSLTU_W GPR:$rs1, GPR:$rs2)>;
// a <= b => !(b < a)
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs2), (v2i32 GPR:$rs1), SETLE)),
(XORI (PMSLT_W GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs2), (v2i32 GPR:$rs1), SETULE)),
(XORI (PMSLTU_W GPR:$rs1, GPR:$rs2), -1)>;
// a > b => b < a
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs2), (v2i32 GPR:$rs1), SETGT)),
(PMSLT_W GPR:$rs1, GPR:$rs2)>;
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs2), (v2i32 GPR:$rs1), SETUGT)),
(PMSLTU_W GPR:$rs1, GPR:$rs2)>;
// a >= b => !(a < b)
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs1), (v2i32 GPR:$rs2), SETGE)),
(XORI (PMSLT_W GPR:$rs1, GPR:$rs2), -1)>;
def: Pat<(v2i32 (setcc (v2i32 GPR:$rs1), (v2i32 GPR:$rs2), SETUGE)),
(XORI (PMSLTU_W GPR:$rs1, GPR:$rs2), -1)>;

// 32-bit logical shift left/right patterns
def: Pat<(v2i32 (shl GPR:$rs1, (v2i32 (splat_vector uimm5:$shamt)))),
(PSLLI_W GPR:$rs1, uimm5:$shamt)>;
Expand Down
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