[AMDGPU][GIsel][NPM] Port AMDGPUGlobalISelDivergenceLowering to NPM - #216657
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keshavvinayak01 merged 2 commits intoAug 17, 2026
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Co-authored-by: GPT-5 <noreply@openai.com> Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha@gmail.com>
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-amdgpu Author: Keshav Vinayak Jha (keshavvinayak01) ChangesPorting Full diff: https://github.com/llvm/llvm-project/pull/216657.diff 9 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index c72fa69aa1419..9fe4123a27bbd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -32,6 +32,13 @@ FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
void initializeAMDGPURegBankCombinerPass(PassRegistry &);
FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
+
+class AMDGPUGlobalISelDivergenceLoweringPass
+ : public RequiredPassInfoMixin<AMDGPUGlobalISelDivergenceLoweringPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
FunctionPass *createAMDGPURegBankSelectPass();
FunctionPass *createAMDGPURegBankLegalizePass();
@@ -211,8 +218,8 @@ extern char &SILowerWWMCopiesLegacyID;
void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
extern char &SILowerI1CopiesLegacyID;
-void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
-extern char &AMDGPUGlobalISelDivergenceLoweringID;
+void initializeAMDGPUGlobalISelDivergenceLoweringLegacyPass(PassRegistry &);
+extern char &AMDGPUGlobalISelDivergenceLoweringLegacyID;
void initializeAMDGPURegBankSelectPass(PassRegistry &);
extern char &AMDGPURegBankSelectID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
index b63419ac82746..40dd6bfcb1a86 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
@@ -19,7 +19,9 @@
#include "AMDGPUGlobalISelUtils.h"
#include "SILowerI1Copies.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/InitializePasses.h"
@@ -29,12 +31,12 @@ using namespace llvm;
namespace {
-class AMDGPUGlobalISelDivergenceLowering : public MachineFunctionPass {
+class AMDGPUGlobalISelDivergenceLoweringLegacy : public MachineFunctionPass {
public:
static char ID;
public:
- AMDGPUGlobalISelDivergenceLowering() : MachineFunctionPass(ID) {}
+ AMDGPUGlobalISelDivergenceLoweringLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -290,26 +292,50 @@ bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
return false;
}
+static bool runDivergenceLowering(MachineFunction &MF, MachineDominatorTree &DT,
+ MachinePostDominatorTree &PDT,
+ MachineUniformityInfo &MUI) {
+ DivergenceLoweringHelper Helper(&MF, &DT, &PDT, &MUI);
+
+ bool Changed = false;
+ // Temporal divergence lowering needs to inspect list of instructions used
+ // outside cycle with divergent exit provided by uniformity analysis. Uniform
+ // instructions from the list require lowering, no instruction is deleted.
+ // Thus it needs to be run before lowerPhis that deletes phis that require
+ // lowering and replaces them with new instructions.
+
+ // Non-i1 temporal divergence lowering.
+ Changed |= Helper.lowerTemporalDivergence();
+ // This covers both uniform and divergent i1s. Lane masks are in sgpr and need
+ // to be updated in each iteration.
+ Changed |= Helper.lowerTemporalDivergenceI1();
+ // Temporal divergence lowering of divergent i1 phi used outside of the cycle
+ // could also be handled by lowerPhis but we do it in lowerTempDivergenceI1
+ // since in some case lowerPhis does unnecessary lane mask merging.
+ Changed |= Helper.lowerPhis();
+ return Changed;
+}
+
} // End anonymous namespace.
-INITIALIZE_PASS_BEGIN(AMDGPUGlobalISelDivergenceLowering, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(AMDGPUGlobalISelDivergenceLoweringLegacy, DEBUG_TYPE,
"AMDGPU GlobalISel divergence lowering", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineUniformityAnalysisPass)
-INITIALIZE_PASS_END(AMDGPUGlobalISelDivergenceLowering, DEBUG_TYPE,
+INITIALIZE_PASS_END(AMDGPUGlobalISelDivergenceLoweringLegacy, DEBUG_TYPE,
"AMDGPU GlobalISel divergence lowering", false, false)
-char AMDGPUGlobalISelDivergenceLowering::ID = 0;
+char AMDGPUGlobalISelDivergenceLoweringLegacy::ID = 0;
-char &llvm::AMDGPUGlobalISelDivergenceLoweringID =
- AMDGPUGlobalISelDivergenceLowering::ID;
+char &llvm::AMDGPUGlobalISelDivergenceLoweringLegacyID =
+ AMDGPUGlobalISelDivergenceLoweringLegacy::ID;
FunctionPass *llvm::createAMDGPUGlobalISelDivergenceLoweringPass() {
- return new AMDGPUGlobalISelDivergenceLowering();
+ return new AMDGPUGlobalISelDivergenceLoweringLegacy();
}
-bool AMDGPUGlobalISelDivergenceLowering::runOnMachineFunction(
+bool AMDGPUGlobalISelDivergenceLoweringLegacy::runOnMachineFunction(
MachineFunction &MF) {
MachineDominatorTree &DT =
getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
@@ -318,23 +344,18 @@ bool AMDGPUGlobalISelDivergenceLowering::runOnMachineFunction(
MachineUniformityInfo &MUI =
getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo();
- DivergenceLoweringHelper Helper(&MF, &DT, &PDT, &MUI);
+ return runDivergenceLowering(MF, DT, PDT, MUI);
+}
- bool Changed = false;
- // Temporal divergence lowering needs to inspect list of instructions used
- // outside cycle with divergent exit provided by uniformity analysis. Uniform
- // instructions from the list require lowering, no instruction is deleted.
- // Thus it needs to be run before lowerPhis that deletes phis that require
- // lowering and replaces them with new instructions.
+PreservedAnalyses AMDGPUGlobalISelDivergenceLoweringPass::run(
+ MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) {
+ MachineDominatorTree &DT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ MachinePostDominatorTree &PDT =
+ MFAM.getResult<MachinePostDominatorTreeAnalysis>(MF);
+ MachineUniformityInfo &MUI = MFAM.getResult<MachineUniformityAnalysis>(MF);
- // Non-i1 temporal divergence lowering.
- Changed |= Helper.lowerTemporalDivergence();
- // This covers both uniform and divergent i1s. Lane masks are in sgpr and need
- // to be updated in each iteration.
- Changed |= Helper.lowerTemporalDivergenceI1();
- // Temporal divergence lowering of divergent i1 phi used outside of the cycle
- // could also be handled by lowerPhis but we do it in lowerTempDivergenceI1
- // since in some case lowerPhis does unnecessary lane mask merging.
- Changed |= Helper.lowerPhis();
- return Changed;
+ if (!runDivergenceLowering(MF, DT, PDT, MUI))
+ return PreservedAnalyses::all();
+
+ return getMachineFunctionPassPreservedAnalyses().preserveSet<CFGAnalyses>();
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 0ab0371705b74..a60ff130b76ba 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -126,6 +126,8 @@ MACHINE_FUNCTION_PASS("amdgpu-rewrite-agpr-copy-mfma", AMDGPURewriteAGPRCopyMFMA
MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass())
MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass())
MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass())
+MACHINE_FUNCTION_PASS("amdgpu-global-isel-divergence-lowering",
+ AMDGPUGlobalISelDivergenceLoweringPass())
MACHINE_FUNCTION_PASS("amdgpu-preload-kern-arg-prolog", AMDGPUPreloadKernArgPrologPass())
MACHINE_FUNCTION_PASS("amdgpu-prepare-agpr-alloc", AMDGPUPrepareAGPRAllocPass())
MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass())
@@ -162,7 +164,6 @@ MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass())
// Global ISel passes
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-prelegalizer-combiner", AMDGPUPreLegalizerCombinerPass())
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner", AMDGPUPostLegalizerCombinerPass())
-DUMMY_MACHINE_FUNCTION_PASS("amdgpu-global-isel-divergence-lowering", AMDGPUGlobalISelDivergenceLoweringPass())
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbankselect", AMDGPURegBankSelectPass())
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbanklegalize", AMDGPURegBankLegalizePass())
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbank-combiner", AMDGPURegBankCombinerPass())
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 6b70838579c62..d43952e1a6e0f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -673,7 +673,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeAMDGPUPrepareAGPRAllocLegacyPass(*PR);
initializeGCNDPPCombineLegacyPass(*PR);
initializeSILowerI1CopiesLegacyPass(*PR);
- initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR);
+ initializeAMDGPUGlobalISelDivergenceLoweringLegacyPass(*PR);
initializeAMDGPURegBankSelectPass(*PR);
initializeAMDGPURegBankLegalizePass(*PR);
initializeSILowerWWMCopiesLegacyPass(*PR);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
index 4a59f6ca48284..9a876e10a8d20 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -passes=amdgpu-global-isel-divergence-lowering -verify-each %s -o - | FileCheck -check-prefix=GFX10 %s
--- |
define void @divergent_i1_phi_uniform_branch() {ret void}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
index f4e6ee0cbc307..3c00dbc2484ef 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -passes=amdgpu-global-isel-divergence-lowering -verify-each %s -o - | FileCheck -check-prefix=GFX10 %s
---
name: divergent_i1_phi_used_outside_loop
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
index 7b2833bc3707d..04c06b1d50e1b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -passes=amdgpu-global-isel-divergence-lowering -verify-each %s -o - | FileCheck -check-prefix=GFX10 %s
---
name: divergent_i1_phi_if_then
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
index f261873770665..4930dc68a475f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -passes=amdgpu-global-isel-divergence-lowering -verify-each %s -o - | FileCheck -check-prefix=GFX10 %s
---
name: temporal_divergent_i1_phi
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
index 9f074c3407981..844e881d5ed61 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgpu10.10-mesa-amdpal -passes=amdgpu-global-isel-divergence-lowering -verify-each %s -o - | FileCheck -check-prefix=GFX10 %s
---
name: temporal_divergent_i32
|
arsenm
reviewed
Aug 17, 2026
Co-authored-by: GPT-5 <noreply@openai.com> Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha@gmail.com>
arsenm
approved these changes
Aug 17, 2026
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Porting
AMDGPUGlobalISelDivergenceLoweringto work with the New PassManager to support GISel.Assisted-by: Codex