Skip to content
Open
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1125,7 +1125,7 @@ class core_ibex_directed_test extends core_ibex_debug_intr_basic_test;
// we are blocking the current instruction until the instruction from WB stage is ready.
wait (dut_vif.dut_cb.ctrl_fsm_cs == FLUSH);
clk_vif.wait_clks(2);
check_priv_mode(PRIV_LVL_M);
check_priv_mode(init_operating_mode);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

When you get an illegal instruction it must trap in M-mode regardless of what the initial operating mode is.

Copy link
Contributor Author

@rickliu2000 rickliu2000 Jul 24, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Well, I think the time of checking was on trap exit. If the design here was to test the mode on trap entry, we'll probably have to discuss how to rewrite this module. The wait on line 1126 here can not capture the flush signal on trap entry. In this specific testcase(riscv_dret_test), the previous functions before the wait line have a handshake mechanism and blocks the wait line until handshake finished, so the first flush on trap entry signal will not be captured in this case. That's probably why I think this checking is wrong.

wait_ret("mret", 15000);
endtask

Expand Down Expand Up @@ -1657,7 +1657,7 @@ class core_ibex_dret_test extends core_ibex_directed_test;

virtual task check_stimulus();
forever begin
wait (dut_vif.dut_cb.dret === 1'b1);
@(negedge dut_vif.dut_cb.dret);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think you're changing what this test does now. This test sees whether there is a DRET instruction and makes sure it is detected as illegal. Have you configured your Ibex to support DRET?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yes I have the dret enabled, and it is only a legal instruction in debug mode.
I don't think I am changing the test here. Somehow, the wait line failed to capture here sometime, only negedge can correctly triggers all the time.

check_illegal_insn("Core did not treat dret like illegal instruction");
end
endtask
Expand Down