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Added ferrocore.lbr
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martonmiklos committed Nov 1, 2019
1 parent 80bb178 commit d74c01b
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8 changes: 8 additions & 0 deletions README.md
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Expand Up @@ -102,3 +102,11 @@ Library for the Ninigi NXW series 2 mm pitch connectors (JST compatible)
Library for the ST ACS110 Overvoltage protected AC switch both SOT-223 and DIL-8 package

https://www.st.com/en/thyristors-scr-and-ac-switches/acs110.html#

# st_viper.lbr - Untested
Library for the ST's Viper series AC/DC converters
Only ST VIPER012HS atm.

# ferrocore.lbr - Untested
Library for Ferrocore SMD coils.
At the moment only contains the DE1207 series (12x12x8mm package)
6 changes: 3 additions & 3 deletions YJ-14015.lbr
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@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.1.3">
<eagle version="9.4.2">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
Expand Down Expand Up @@ -179,7 +179,7 @@ It features onboard oscillator (both main &amp; low power 32.768 Hz), and integr
<pin name="P0.14" x="27.94" y="-5.08" visible="pin" length="middle" rot="R180"/>
<pin name="P0.15" x="27.94" y="-2.54" visible="pin" length="middle" rot="R180"/>
<pin name="P0.16" x="27.94" y="0" visible="pin" length="middle" rot="R180"/>
<pin name="SWDIO/NRESET" x="27.94" y="2.54" visible="pin" length="middle" rot="R180"/>
<pin name="SWDIO/!RESET" x="27.94" y="2.54" visible="pin" length="middle" rot="R180"/>
<pin name="SWDCLK" x="27.94" y="5.08" visible="pin" length="middle" direction="in" rot="R180"/>
<pin name="P0.17" x="27.94" y="7.62" visible="pin" length="middle" rot="R180"/>
<pin name="P0.18" x="27.94" y="10.16" visible="pin" length="middle" rot="R180"/>
Expand Down Expand Up @@ -241,7 +241,7 @@ It features onboard oscillator (both main &amp; low power 32.768 Hz), and integr
<connect gate="G$1" pin="P0.29" pad="P.29"/>
<connect gate="G$1" pin="P0.30" pad="P.30"/>
<connect gate="G$1" pin="SWDCLK" pad="SWDCLK"/>
<connect gate="G$1" pin="SWDIO/NRESET" pad="SWDIO"/>
<connect gate="G$1" pin="SWDIO/!RESET" pad="SWDIO"/>
<connect gate="G$1" pin="VDD" pad="VDD"/>
</connects>
<technologies>
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