Building a Traffic Light Controller with Verilog

Simple projects are a great way to learn Verilog. This project marks my first steps with the Sipeed Tang Primer 20K FPGA, exploring its programming and practical operation.

1. Description

The Verilog code implements the traffic light control logic, defining the LED activation sequence. This sequence is generated by a counter that cycles through the different states, ensuring:

Sequential LED control (red → yellow → green → red)

Precise timing for each light phase

Automatic cycling (no reset required)

2. Repository Structure

• assets/ - Images and video

• constraints/ - Pin constraint files

• src/ - Verilog source code

• tb/ - Testbench code

3. Project Structure

The traffic light sequence follows a cycle where each LED stays on for 1 second and off for 0.5 seconds, as illustrated in the flowchart below:

4. Bill of Materials

• Sipeed Tang Primer 20K (FPGA based on Gowin GW2A-LV18PG256C8/I7)

• 3 resistors of 10Ω to limit the LED current

• 3 LEDs to represent the traffic light colors

• 4 M-M jumper wires

• 1 breadboard

• USB-C cable

5. Schematic Diagram

Below is the electrical schematic showing the LED connections to the FPGA.

6. Verilog Code and Constraints

Available in the src and constraints directories.

7. Synthesis and Programming

To compile and load the code onto the FPGA, I used the Gowin IDE tool. The process was as follows:

1. Create a new project and set the GW2A-LV18PG256C8/I7 as the target.

2. Specify the correct LED pins in the constraints file (.cst).

3. Compile, synthesize, and load the bitstream onto the FPGA.

4. With the code running, the LEDs automatically alternate between red, green, and yellow.

8. Results

Click the image below for a short video showing the traffic light controller in operation, demonstrating the expected system behavior as it cycles through the light sequence:

9. Conclusion

This simple project demonstrates how Verilog can be used to control LEDs on an FPGA. The Tang Primer 20K proved to be an excellent platform for learning.

10. Technologies Used

• FPGA: Sipeed Tang Primer 20K (GW2A-LV18PG256C8/I7) with Dock

• HDL: Verilog

• Development Tool: Gowin IDE

• Schematic Design: Fritzing