snp guest vsm: register intercepts #1142

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sluck-msft wants to merge 11 commits into microsoft:main from sluck-msft:gvsm/cr-intercepts

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sluck-msft commented Apr 4, 2025

Support for VTL 1 to register for write intercepts on certain registers.

Tested:

SNP + Guest VSM boots no debugger
SNP boots

sluck-msft requested review from jstarks and smalis-msft

April 4, 2025 16:47

sluck-msft requested a review from a team as a code owner

April 4, 2025 16:47

sluck-msft force-pushed the gvsm/cr-intercepts branch from 85ab7fa to af56d64 Compare

April 4, 2025 17:18

smalis-msft reviewed

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sluck-msft force-pushed the gvsm/cr-intercepts branch from 0eead15 to 2c05abc Compare

April 8, 2025 18:40

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sluck-msft added 4 commits

April 8, 2025 16:37


          sketch cr0 and cr4 intercept handling

6a59f08


          add tr registers and make the vtl 1 apic software enabled

f12c602


          cleanup

50906ec


          get intercept control registers

01efbd9

sluck-msft added 5 commits

April 8, 2025 16:39


          control msr writes

6270cde


          other cases

b57175d


          cleanup

b3c5722


          feedback

d8d4755


          feedback

fa71c45

sluck-msft force-pushed the gvsm/cr-intercepts branch from 9c2582d to fa71c45 Compare

April 9, 2025 00:10

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          feedback - try to get rid of extra enum

65da247

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          cleanup

b7db4a1

sluck-msft dismissed smalis-msft’s stale review via

b7db4a1

April 9, 2025 20:17

sluck-msft commented

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openhcl/virt_mshv_vtl/src/lib.rs

+                          // The APIC is software-enabled after reset for
+                          // secure VTLs, to maintain compatibility with released versions of secure
+                          // kernel
+                          let mut lapic = apic_set.add_apic(vp_info, vtl == Vtl::Vtl1);

Contributor Author

sluck-msft Apr 9, 2025

@jstarks any concerns with this part of the change? Our other components also do this; without it, if I remember correctly, I couldn't get the intercept delivered to VTL 1.

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openhcl/virt_mshv_vtl/src/processor/hardware_cvm/mod.rs

+                              hvdef::HV_SYNIC_INTERCEPTION_SINT_INDEX,
+                              &crate::processor::InterceptMessageType::Register { reg, value }
+                                  .generate_hv_message(self.vp_index(), vtl, message_state),
+                          );

Contributor Author

sluck-msft Apr 9, 2025

@jstarks also wanted to confirm with you that this post_message approach is correct for sending intercepts to VTL 1.

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