cache: flush cache on reset #22
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Right now, this core does not do anything special on reset to the memory backing the instruction and data caches. After asserting
ResetSignal(), the caches remain intact.I'm using the reset signal to stop the processor, load a new program, and restart the processor with the new program. Since the caches are intact, this can lead to the core running a mix of stale and new code.
To avoid this, I think it makes sense for the caches to flush themselves on reset. I've chosen to do this by initializing the caches in the
"FLUSH"state. This works with the designs I'm using and passes the test suite, but I'd like a second opinion on this solution. This fix also adds a few dozen cycles of delay between reset and the first instruction fetch, but I think that's unavoidable.I've also added a commit to get the formal tests running with Amaranth 0.5.7 and recent Yosys.