Skip to content

Improve immediate types of instructions #532

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
nazar-pc merged 3 commits into from
Jan 22, 2026
Merged

Improve immediate types of instructions #532

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
df1ca35
Simplify tests a bit
nazar-pc Jan 21, 2026
f9696b2
Add missing `build.rs` inclusion in `Cargo.toml`
nazar-pc Jan 21, 2026
93c233b
Improve immediate types of instructions
nazar-pc Jan 22, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions crates/execution/ab-riscv-benchmarks/Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ authors = ["Nazar Mokrynskyi <nazar@mokrynskyi.com>"]
edition = "2024"
include = [
"/src",
"/build.rs",
"/Cargo.toml",
]

Expand Down
1 change: 1 addition & 0 deletions crates/execution/ab-riscv-interpreter/Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ authors = ["Nazar Mokrynskyi <nazar@mokrynskyi.com>"]
edition = "2024"
include = [
"/src",
"/build.rs",
"/Cargo.toml",
]
links = "ab-riscv-interpreter"
Expand Down
80 changes: 40 additions & 40 deletions crates/execution/ab-riscv-interpreter/src/rv64.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -189,57 +189,57 @@ where

Self::Addw { rd, rs1, rs2 } => {
let sum = (state.regs.read(rs1) as i32).wrapping_add(state.regs.read(rs2) as i32);
state.regs.write(rd, (sum as i64).cast_unsigned());
state.regs.write(rd, i64::from(sum).cast_unsigned());
}
Self::Subw { rd, rs1, rs2 } => {
let diff = (state.regs.read(rs1) as i32).wrapping_sub(state.regs.read(rs2) as i32);
state.regs.write(rd, (diff as i64).cast_unsigned());
state.regs.write(rd, i64::from(diff).cast_unsigned());
}
Self::Sllw { rd, rs1, rs2 } => {
let shamt = state.regs.read(rs2) & 0x1f;
let shifted = (state.regs.read(rs1) as u32) << shamt;
state
.regs
.write(rd, (shifted.cast_signed() as i64).cast_unsigned());
.write(rd, i64::from(shifted.cast_signed()).cast_unsigned());
}
Self::Srlw { rd, rs1, rs2 } => {
let shamt = state.regs.read(rs2) & 0x1f;
let shifted = (state.regs.read(rs1) as u32) >> shamt;
state
.regs
.write(rd, (shifted.cast_signed() as i64).cast_unsigned());
.write(rd, i64::from(shifted.cast_signed()).cast_unsigned());
}
Self::Sraw { rd, rs1, rs2 } => {
let shamt = state.regs.read(rs2) & 0x1f;
let shifted = (state.regs.read(rs1) as i32) >> shamt;
state.regs.write(rd, (shifted as i64).cast_unsigned());
state.regs.write(rd, i64::from(shifted).cast_unsigned());
}

Self::Addi { rd, rs1, imm } => {
let value = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
state.regs.write(rd, value);
}
Self::Slti { rd, rs1, imm } => {
let value = state.regs.read(rs1).cast_signed() < (imm as i64);
let value = state.regs.read(rs1).cast_signed() < i64::from(imm);
state.regs.write(rd, value as u64);
}
Self::Sltiu { rd, rs1, imm } => {
let value = state.regs.read(rs1) < ((imm as i64).cast_unsigned());
let value = state.regs.read(rs1) < i64::from(imm).cast_unsigned();
state.regs.write(rd, value as u64);
}
Self::Xori { rd, rs1, imm } => {
let value = state.regs.read(rs1) ^ ((imm as i64).cast_unsigned());
let value = state.regs.read(rs1) ^ i64::from(imm).cast_unsigned();
state.regs.write(rd, value);
}
Self::Ori { rd, rs1, imm } => {
let value = state.regs.read(rs1) | ((imm as i64).cast_unsigned());
let value = state.regs.read(rs1) | i64::from(imm).cast_unsigned();
state.regs.write(rd, value);
}
Self::Andi { rd, rs1, imm } => {
let value = state.regs.read(rs1) & ((imm as i64).cast_unsigned());
let value = state.regs.read(rs1) & i64::from(imm).cast_unsigned();
state.regs.write(rd, value);
}
Self::Slli { rd, rs1, shamt } => {
Expand All @@ -256,79 +256,79 @@ where
}

Self::Addiw { rd, rs1, imm } => {
let sum = (state.regs.read(rs1) as i32).wrapping_add(imm);
state.regs.write(rd, (sum as i64).cast_unsigned());
let sum = (state.regs.read(rs1) as i32).wrapping_add(i32::from(imm));
state.regs.write(rd, i64::from(sum).cast_unsigned());
}
Self::Slliw { rd, rs1, shamt } => {
let shifted = (state.regs.read(rs1) as u32) << shamt;
state
.regs
.write(rd, (shifted.cast_signed() as i64).cast_unsigned());
.write(rd, i64::from(shifted.cast_signed()).cast_unsigned());
}
Self::Srliw { rd, rs1, shamt } => {
let shifted = (state.regs.read(rs1) as u32) >> shamt;
state
.regs
.write(rd, (shifted.cast_signed() as i64).cast_unsigned());
.write(rd, i64::from(shifted.cast_signed()).cast_unsigned());
}
Self::Sraiw { rd, rs1, shamt } => {
let shifted = (state.regs.read(rs1) as i32) >> shamt;
state.regs.write(rd, (shifted as i64).cast_unsigned());
state.regs.write(rd, i64::from(shifted).cast_unsigned());
}

Self::Lb { rd, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
let value = state.memory.read::<i8>(addr)? as i64;
.wrapping_add(i64::from(imm).cast_unsigned());
let value = i64::from(state.memory.read::<i8>(addr)?);
state.regs.write(rd, value.cast_unsigned());
}
Self::Lh { rd, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
let value = state.memory.read::<i16>(addr)? as i64;
.wrapping_add(i64::from(imm).cast_unsigned());
let value = i64::from(state.memory.read::<i16>(addr)?);
state.regs.write(rd, value.cast_unsigned());
}
Self::Lw { rd, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
let value = state.memory.read::<i32>(addr)? as i64;
.wrapping_add(i64::from(imm).cast_unsigned());
let value = i64::from(state.memory.read::<i32>(addr)?);
state.regs.write(rd, value.cast_unsigned());
}
Self::Ld { rd, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
let value = state.memory.read::<u64>(addr)?;
state.regs.write(rd, value);
}
Self::Lbu { rd, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
let value = state.memory.read::<u8>(addr)?;
state.regs.write(rd, value as u64);
}
Self::Lhu { rd, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
let value = state.memory.read::<u16>(addr)?;
state.regs.write(rd, value as u64);
}
Self::Lwu { rd, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
let value = state.memory.read::<u32>(addr)?;
state.regs.write(rd, value as u64);
}
Expand All @@ -337,7 +337,7 @@ where
let target = (state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned()))
.wrapping_add(i64::from(imm).cast_unsigned()))
& !1u64;
state.regs.write(rd, state.instruction_fetcher.get_pc());
return state
Expand All @@ -350,28 +350,28 @@ where
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
state.memory.write(addr, state.regs.read(rs2) as u8)?;
}
Self::Sh { rs2, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
state.memory.write(addr, state.regs.read(rs2) as u16)?;
}
Self::Sw { rs2, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
state.memory.write(addr, state.regs.read(rs2) as u32)?;
}
Self::Sd { rs2, rs1, imm } => {
let addr = state
.regs
.read(rs1)
.wrapping_add((imm as i64).cast_unsigned());
.wrapping_add(i64::from(imm).cast_unsigned());
state.memory.write(addr, state.regs.read(rs2))?;
}

Expand All @@ -385,7 +385,7 @@ where
.instruction_fetcher
.set_pc(
&mut state.memory,
old_pc.wrapping_add((imm as i64).cast_unsigned()),
old_pc.wrapping_add(i64::from(imm).cast_unsigned()),
)
.map_err(ExecutionError::from);
}
Expand All @@ -400,7 +400,7 @@ where
.instruction_fetcher
.set_pc(
&mut state.memory,
old_pc.wrapping_add((imm as i64).cast_unsigned()),
old_pc.wrapping_add(i64::from(imm).cast_unsigned()),
)
.map_err(ExecutionError::from);
}
Expand All @@ -415,7 +415,7 @@ where
.instruction_fetcher
.set_pc(
&mut state.memory,
old_pc.wrapping_add((imm as i64).cast_unsigned()),
old_pc.wrapping_add(i64::from(imm).cast_unsigned()),
)
.map_err(ExecutionError::from);
}
Expand All @@ -430,7 +430,7 @@ where
.instruction_fetcher
.set_pc(
&mut state.memory,
old_pc.wrapping_add((imm as i64).cast_unsigned()),
old_pc.wrapping_add(i64::from(imm).cast_unsigned()),
)
.map_err(ExecutionError::from);
}
Expand All @@ -445,7 +445,7 @@ where
.instruction_fetcher
.set_pc(
&mut state.memory,
old_pc.wrapping_add((imm as i64).cast_unsigned()),
old_pc.wrapping_add(i64::from(imm).cast_unsigned()),
)
.map_err(ExecutionError::from);
}
Expand All @@ -460,14 +460,14 @@ where
.instruction_fetcher
.set_pc(
&mut state.memory,
old_pc.wrapping_add((imm as i64).cast_unsigned()),
old_pc.wrapping_add(i64::from(imm).cast_unsigned()),
)
.map_err(ExecutionError::from);
}
}

Self::Lui { rd, imm } => {
state.regs.write(rd, (imm as i64).cast_unsigned());
state.regs.write(rd, i64::from(imm).cast_unsigned());
}

Self::Auipc { rd, imm } => {
Expand All @@ -477,7 +477,7 @@ where
.wrapping_sub(self.size().into());
state
.regs
.write(rd, old_pc.wrapping_add((imm as i64).cast_unsigned()));
.write(rd, old_pc.wrapping_add(i64::from(imm).cast_unsigned()));
}

Self::Jal { rd, imm } => {
Expand All @@ -488,7 +488,7 @@ where
.instruction_fetcher
.set_pc(
&mut state.memory,
old_pc.wrapping_add((imm as i64).cast_unsigned()),
old_pc.wrapping_add(i64::from(imm).cast_unsigned()),
)
.map_err(ExecutionError::from);
}
Expand Down
20 changes: 10 additions & 10 deletions crates/execution/ab-riscv-interpreter/src/rv64/b/zba/tests.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
use crate::rv64::test_utils::{execute, initialize_test_instruction_state};
use crate::rv64::test_utils::{execute, initialize_state};
use ab_riscv_primitives::instruction::rv64::b::zba::Rv64ZbaInstruction;
use ab_riscv_primitives::registers::EReg;

#[test]
fn test_add_uw() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::AddUw {
let mut state = initialize_state([Rv64ZbaInstruction::AddUw {
rd: EReg::A2,
rs1: EReg::A0,
rs2: EReg::A1,
Expand All @@ -21,7 +21,7 @@ fn test_add_uw() {

#[test]
fn test_sh1add() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::Sh1add {
let mut state = initialize_state([Rv64ZbaInstruction::Sh1add {
rd: EReg::A2,
rs1: EReg::A0,
rs2: EReg::A1,
Expand All @@ -38,7 +38,7 @@ fn test_sh1add() {

#[test]
fn test_sh2add() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::Sh2add {
let mut state = initialize_state([Rv64ZbaInstruction::Sh2add {
rd: EReg::A2,
rs1: EReg::A0,
rs2: EReg::A1,
Expand All @@ -55,7 +55,7 @@ fn test_sh2add() {

#[test]
fn test_sh3add() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::Sh3add {
let mut state = initialize_state([Rv64ZbaInstruction::Sh3add {
rd: EReg::A2,
rs1: EReg::A0,
rs2: EReg::A1,
Expand All @@ -72,7 +72,7 @@ fn test_sh3add() {

#[test]
fn test_sh1add_uw() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::Sh1addUw {
let mut state = initialize_state([Rv64ZbaInstruction::Sh1addUw {
rd: EReg::A2,
rs1: EReg::A0,
rs2: EReg::A1,
Expand All @@ -89,7 +89,7 @@ fn test_sh1add_uw() {

#[test]
fn test_sh2add_uw() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::Sh2addUw {
let mut state = initialize_state([Rv64ZbaInstruction::Sh2addUw {
rd: EReg::A2,
rs1: EReg::A0,
rs2: EReg::A1,
Expand All @@ -106,7 +106,7 @@ fn test_sh2add_uw() {

#[test]
fn test_sh3add_uw() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::Sh3addUw {
let mut state = initialize_state([Rv64ZbaInstruction::Sh3addUw {
rd: EReg::A2,
rs1: EReg::A0,
rs2: EReg::A1,
Expand All @@ -123,7 +123,7 @@ fn test_sh3add_uw() {

#[test]
fn test_slli_uw() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::SlliUw {
let mut state = initialize_state([Rv64ZbaInstruction::SlliUw {
rd: EReg::A2,
rs1: EReg::A0,
shamt: 4,
Expand All @@ -139,7 +139,7 @@ fn test_slli_uw() {

#[test]
fn test_slli_uw_max_shamt() {
let mut state = initialize_test_instruction_state([Rv64ZbaInstruction::SlliUw {
let mut state = initialize_state([Rv64ZbaInstruction::SlliUw {
rd: EReg::A2,
rs1: EReg::A0,
shamt: 63,
Expand Down
Loading