minor update

nqdtan · Apr 8, 2023 · 61ce49b · 61ce49b
1 parent 94eaf1d
commit 61ce49b
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Showing 6 changed files with 15 additions and 63 deletions.
diff --git a/README.md b/README.md
@@ -9,11 +9,11 @@ To facilitate some customizability, the examples shown here can be built with Vi
 
 ## Development Environment
 
-**Base platform**: xilinx_vck5000_gen3x16_xdma_1_202120_1
+**Base platform**: xilinx_vck5000_gen4x8_qdma_2_202220_1
 
-**Vitis**: 2021.2
+**Vitis**: 2022.2
 
-**XRT**: 2.12.447 (2021.2)
+**XRT**: 2.14.384 (2022.2)
 
 **Linux kernel**: 5.4.0-42-generic
 
@@ -57,7 +57,7 @@ This simple example demonstrates how to configure a PL kernel (vecadd) to perfor
   make ulp_bd top=vecadd
   
   # Build Vivado Reconfigurable Module Project (PR flow). This flow will synthesize,
-  # P&R the ulp and link it with the static blp (hw_bb_locked.dcp)
+  # P&R the ulp and link it with the static blp (xilinx_vck5000_gen4x8_qdma_2_202220_1_bb_locked.dcp)
   make rm_project top=vecadd
 ```
 
@@ -109,7 +109,7 @@ This simple example demonstrates how to configure the AIE (Tile core, Tile DMA,
   make ulp_bd top=data_mover_mm2mm aie=1
   
   # Build Vivado Reconfigurable Module Project (PR flow). This flow will synthesize,
-  # P&R the ulp and link it with the static blp (hw_bb_locked.dcp)
+  # P&R the ulp and link it with the static blp (xilinx_vck5000_gen4x8_qdma_2_202220_1_bb_locked.dcp)
   make rm_project top=data_mover_mm2mm
 ```
 

diff --git a/build_rm_project.tcl b/build_rm_project.tcl
@@ -2,8 +2,6 @@ set project_name [lindex $argv 0]
 set kernel [lindex $argv 1]
 set jobs [lindex $argv 2]
 
-set_param board.repoPaths /tools/C/tan.nqd/vck5000_board_files
-
 create_project -force $project_name $project_name -part xcvc1902-vsvd1760-2MP-e-S
 set_property board_part xilinx.com:vck5000:part0:1.0 [current_project]
 

diff --git a/constrs/_user_impl_clk.xdc b/constrs/_user_impl_clk.xdc
@@ -1,3 +1,11 @@
 
 # Kernel clock overridden by user
-create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 151 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
+# kernel0_freq = (33.33 MHz / _divide_factor) * _multiply_factor
+# 500 MHz
+create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 150 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
+# 400 MHz
+create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 120 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
+# 300 MHz
+create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 90 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
+# 200 MHz
+create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 60 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0
diff --git a/ulp_bd.tcl b/ulp_bd.tcl
@@ -30,8 +30,6 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
    return 1
 }
 
-#set_param board.repoPaths /tools/C/tan.nqd/vck5000_board_files
-
 ################################################################
 # START
 ################################################################

diff --git a/xclbin_generator/appendSection.json b/xclbin_generator/appendSection.json
diff --git a/xclbin_generator/mem_topology.json b/xclbin_generator/mem_topology.json
@@ -1,20 +1,13 @@
 {
     "mem_topology": {
-        "m_count": "2",
+        "m_count": "1",
         "m_mem_data": [
             {
                 "m_type": "MEM_DDR4",
                 "m_used": "1",
                 "m_sizeKB": "0xc00000",
                 "m_tag": "MC_NOC0",
                 "m_base_address": "0xc100000000"
-            },
-            {
-                "m_type": "MEM_DRAM",
-                "m_used": "0",
-                "m_sizeKB": "0x80",
-                "m_tag": "BRAM",
-                "m_base_address": "0x20204000000"
             }
         ]
     }