PDP11: Add KWV11-A/C programmable clock

[pixitha]

Summary

Add a SIMH model of the DEC KWV11-A/C Q-bus programmable real-time clock.
The device is disabled by default and uses SIMH Q-bus auto-configuration.

The implementation provides:

• CSR and BPR register handling at the configured KWV11 address;
• the KWV11 operating modes and selectable counter rates;
• word and byte access behavior for the CSR and BPR;
• counter overflow, repeat, flag-overrun, and ST1/ST2 maintenance behavior;
• separate overflow and ST2 interrupt vectors; and
• 50 Hz and 60 Hz line-frequency configuration.

The existing PDP-11 CMake and legacy makefile source lists, device table, and
auto-configuration table are updated to include the new device.

Validation

The in-tree PDP-11 test script was run with the built simulator:

./BIN/pdp11 PDP11/tests/pdp11_test.ini

The test covers BPR byte-lane behavior, preset and one-shot overflow, repeated
overflow reload, ST2 capture, external-event modes, autonomous oscillator
operation, both interrupt vectors, and 50/60 Hz configuration. The completed
run ended with:

** KWV11: autonomous 60 Hz line clock

HALT instruction, PC: 001002 (HALT)
!! All KWV11 Tests Passed !!

Initial compilation was also completed on macOS arm64 and in an Ubuntu Docker
arm environment. The same PDP-11 CTest target was then built and run on Linux
x86-64:

cmake --build build --target pdp11 -j2
ctest --test-dir build --output-on-failure -R simh-pdp11

Result: 1/1 test passed.

As an additional guest-level check, a small RT-11 program executed real PDP-11
instructions against the device and reported:

KWV11 standalone guest probe
Reset CSR= 000000 BPR= 000000
BPR low-byte write -> 000123
BPR high-byte write -> 022400
Started 1 kHz repeat, CSR= 000043
1 kHz overflow, CSR= 000243 BPR= 177754
ST2 capture, CSR= 100043 BPR= 012345
CSR after read-clear= 000043
Probe complete

AI-assisted development disclosure

OpenAI ChatGPT/Codex (Luna and Terra) generated and revised portions of the C
implementation, tests, comments, and documentation under Kyle Duren's
direction. Kyle Duren reviewed the final changes, performed the validation
described above, and accepts responsibility for the submitted contribution.

References

The register layout, operating modes, counter rates, maintenance inputs,
interrupt vectors, and access behavior were checked against:

• DEC, ADV11-A, KWV11-A, AAV11-A, DRV11 User's Manual,
  EK-ADV11-OP-002, 3rd printing (revised April 1977),
  Bitsavers PDF,
  especially printed pp. 3-1, 3-3, 3-5, 3-8, 3-9, and 3-11--3-12 (PDF
  pp. 30, 32, 34, 37, 38, and 40--41);
• DEC, KWV11A Diagnostic, MAINDEC-11-CNKWA-A, CNKWAA0, AH-T452A-MC
  (May 1983), Bitsavers scan,
  especially listing pp. 58--62 for BPR word tests, CSR low/high-byte tests,
  and counter-to-BPR transfer; and
• the existing SIMH programmable-clock implementation conventions.

[markpizz]

Hi there Kyle,

Thanks for doing the work (with your indicated helper) to add this device to the PDP11 simulator.

It has been merged into the https://github.com/simh/simh repository with 2 changes:

1. Line 263 of pdp11_kmv11.c has been changed to add a (uint32) cast to the second argument of the sim_activate_after() routine.
2. The line endings of the pdp11_kmv11.c source module have been changed to CRLF to be consistent with the rest of the simh codebase.

ALSO, Thank you VERY MUCH for being the first to add any build time test in the PDP11 that exercises the newly added device.