cv32e20: Enable Performance Optimizations and Simulation Control Knobs

[Amit-Matth]

Description

This PR addresses the simulation slowdown observed when the RVFI Analysis Port is enabled (Issue #12). It introduces control knobs and logic improvements to significantly reduce simulation overhead, particularly for DSim.

Key Changes

1. Intelligent Analysis Port Enablement:

   • Updated uvmt_cv32e20_general_purpose_test.sv to only enable writing to the RVFI Analysis Port (ap_write_en) when it is strictly necessary (i.e., when cov_model_enabled or scoreboard_enabled is true).
   • This prevents millions of redundant transactions from being generated during simulation runs where they are not consumed.

2. New Performance Control Knobs (Plusargs):

   • +scoreboard_enabled=0: Allows users to explicitly disable the scoreboard to save simulation cycles during debug or regression.
   • +NO_ISS: Allows disabling the ISS (Instruction Set Simulator) Reference Model override (Spike) for pure RTL simulation speed.

3. Build System & Style Sync:

   • Minor updates to mk/Common.mk and mk/uvmt/uvmt.mk to align with the performance configuration and coding style.

Performance Impact

When combined with the corresponding optimizations in core-v-verif (Sparse CSR Monitoring), we observe significant speedups:

• hello-world: ~1.18x speedup
• dhrystone: ~1.41x speedup

Dependencies

• This PR pairs with the optimization fixes in core-v-verif (Sparse CSR monitoring logic in uvma_rvfi_instr_mon).

[MikeOpenHWGroup]

Hi @Amit-Matth, thanks very much for this PR. May I ask for you to target it towards the dev branch? I will give it a full review then. Thanks!