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Add Support for Digilent Arty-A7 100T FPGA Board #2581
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For reference, here is the forked software stack: https://github.com/WorldofJARcraft/cva6-sdk |
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👋 Hi there! This pull request seems inactive. Need more help or have updates? Feel free to let us know. If there are no updates within the next few days, we'll go ahead and close this PR. 😊 |
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This patch adds support for the Arty A7 FPGA (#154).
Overview
Changed
What I have been able to test so far:
west debug
andwest flash
in both 32 and 64 bit configs and runs as expected (zephyr PR coming soon)CVA6ConfigFpgaEn
, i.e., inferring memories as block RAM, meets timing and fits the board with appx. 5000 LUTs to spare.What I have not yet tested:
What does not work:
CVA6ConfigFpgaEn
) does not fit the board, uses appx. 1000 LUTs too much. Might fit when sacrificing a peripheral (e.g., debug, SPI, GPIO, ...)