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    63 repositories

    • cvw

      Public
      CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, …
      SystemVerilog
      •
      Other
      •389•484•23•7•Updated Feb 11, 2026Feb 11, 2026

    • cva6

      Public
      The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of bo…
      asiccpufpgarisc-vsystemverilog-hdlrv64gcariane
      Assembly
      •
      Other
      •880•2.8k•235•8•Updated Feb 10, 2026Feb 10, 2026

    • cve2

      Public
      The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work f…
      SystemVerilog
      •
      Apache License 2.0
      •685•57•152•11•Updated Feb 9, 2026Feb 9, 2026

    • cvfpu-uvm

      Public
      UVM Verification Environment for the CVFPU
      Perl
      •
      Other
      •5•9•1•0•Updated Feb 6, 2026Feb 6, 2026

    • cv-hpdcache

      Public
      RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
      SystemVerilog
      •
      Other
      •41•98•4•4•Updated Feb 6, 2026Feb 6, 2026

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      verificationsystemveriloguvmrisc-v
      Assembly
      •
      Other
      •303•655•131•54•Updated Feb 4, 2026Feb 4, 2026

    • cv32e20-dv

      Public
      Assembly
      •
      Apache License 2.0
      •11•3•2•5•Updated Feb 1, 2026Feb 1, 2026

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •
      GNU General Public License v2.0
      •88•78•37•5•Updated Jan 28, 2026Jan 28, 2026

    • meta-cva6-yocto

      Public
      Yocto layer for CVA6
      BitBake
      •
      MIT License
      •6•5•0•2•Updated Jan 26, 2026Jan 26, 2026

    • tristan-isolde-unified-access-page

      Public
      Unified RISC-V Access Platform project repository
      JavaScript
      •
      Eclipse Public License 2.0
      •44•21•2•4•Updated Jan 12, 2026Jan 12, 2026

    • programs

      Public
      Documentation for the OpenHW Group's set of CORE-V RISC-V cores
      HTML
      •
      Other
      •98•223•9•9•Updated Jan 11, 2026Jan 11, 2026

    • cv-hpdcache-verif

      Public
      Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
      SystemVerilog
      •
      Apache License 2.0
      •8•20•0•1•Updated Jan 6, 2026Jan 6, 2026

    • cva6-safe

      Public
      A dual-core lockstep (DCLS) subsystem for the CVA6. Also supports dual-core asymmetric multi-processing (AMP) when lockstep in not needed.
      Other
      •1•0•0•1•Updated Dec 15, 2025Dec 15, 2025

    • core-v-mcu

      Public
      This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
      microcontrollerriscvsystemverilogopenhwgroup
      SystemVerilog
      •
      Other
      •68•196•77•9•Updated Dec 11, 2025Dec 11, 2025

    • openhwfoundation.org

      Public
      OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provid…
      hugowebdev
      HTML
      •
      Eclipse Public License 2.0
      •11•19•7•4•Updated Nov 28, 2025Nov 28, 2025

    • cvw-arch-verif

      Public
      The purpose of the repo is to support CORE-V Wally architectural verification
      SystemVerilog
      •
      Other
      •39•17•19•1•Updated Nov 11, 2025Nov 11, 2025

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •148•569•40•13•Updated Oct 21, 2025Oct 21, 2025

    • u-boot

      Public
      Unofficial development fork of U-Boot
      C
      •19•1•1•0•Updated Oct 15, 2025Oct 15, 2025

    • cva5

      Public
      The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
      SystemVerilog
      •
      Apache License 2.0
      •29•127•4•0•Updated Jul 11, 2025Jul 11, 2025

    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      riscvriscv32imfc
      SystemVerilog
      •
      Other
      •499•1.2k•54•11•Updated May 26, 2025May 26, 2025

    • osdforum.org

      Public
      The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and l…
      hugowebdev
      HTML
      •
      Eclipse Public License 2.0
      •6•1•0•0•Updated Apr 22, 2025Apr 22, 2025

    • core-v-sw

      Public
      Main Repo for the OpenHW Group Software Task Group
      Eclipse Public License 2.0
      •28•17•5•0•Updated Mar 11, 2025Mar 11, 2025

    • cv-mesh

      Public
      Verilog
      •0•4•0•0•Updated Mar 10, 2025Mar 10, 2025

    • core-v-cores

      Public
      CORE-V Family of RISC-V Cores
      23•326•1•1•Updated Feb 13, 2025Feb 13, 2025

    • cv32e40s-dv

      Public
      CV32E40S Design-Verification environment
      Assembly
      •
      Apache License 2.0
      •1•0•1•0•Updated Nov 11, 2024Nov 11, 2024

    • cv32e40x

      Public
      4 stage, in-order, compute RISC-V core based on the CV32E40P
      SystemVerilog
      •
      Other
      •55•258•32•5•Updated Nov 6, 2024Nov 6, 2024

    • cv32e40s

      Public
      4 stage, in-order, secure RISC-V core based on the CV32E40P
      SystemVerilog
      •
      Other
      •29•155•3•2•Updated Oct 31, 2024Oct 31, 2024

    • corev-qemu

      Public
      Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use rele…
      C
      •
      Other
      •6.5k•1•0•2•Updated Aug 16, 2024Aug 16, 2024

    • core-v-polara-apu

      Public
      The OpenPiton Platform
      Assembly
      •258•17•0•2•Updated Aug 14, 2024Aug 14, 2024

    • corev-binutils-gdb

      Public
      C
      •
      GNU General Public License v2.0
      •28•9•4•0•Updated Jul 30, 2024Jul 30, 2024