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    298 repositories

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •36•42•7•4•Updated Mar 13, 2025Mar 13, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •13•47•1•4•Updated Mar 13, 2025Mar 13, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •10•62•1•1•Updated Mar 13, 2025Mar 13, 2025

    • control-pulp

      Public
      C
      •
      Other
      •2•3•1•1•Updated Mar 13, 2025Mar 13, 2025

    • safety_island

      Public
      A reliable, real-time subsystem for the Carfield SoC
      C
      •
      Other
      •4•14•1•4•Updated Mar 13, 2025Mar 13, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •47•288•3•5•Updated Mar 12, 2025Mar 12, 2025

    • chimera

      Public
      Python
      •
      Other
      •3•16•9•3•Updated Mar 12, 2025Mar 12, 2025

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •4•11•1•4•Updated Mar 12, 2025Mar 12, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •60•69•16•7•Updated Mar 12, 2025Mar 12, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •12•26•8•4•Updated Mar 12, 2025Mar 12, 2025

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•10•0•2•Updated Mar 12, 2025Mar 12, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •21•99•1•4•Updated Mar 12, 2025Mar 12, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •23•82•5•3•Updated Mar 11, 2025Mar 11, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •140•406•70•6•Updated Mar 11, 2025Mar 11, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •11•12•5•3•Updated Mar 11, 2025Mar 11, 2025

    • pulp-dronet

      Public
      A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP
      deep-learningcnnartificial-intelligenceriscvautonomous-quadcoptorpulpclosed-loop-controlend-to-end-learningnano-uav
      C
      •
      Apache License 2.0
      •165•527•2•0•Updated Mar 10, 2025Mar 10, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •16•6•0•6•Updated Mar 10, 2025Mar 10, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •70•1•0•3•Updated Mar 10, 2025Mar 10, 2025

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •547•0•0•2•Updated Mar 10, 2025Mar 10, 2025

    • neureka

      Public
      2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
      SystemVerilog
      •
      Other
      •4•21•5•2•Updated Mar 10, 2025Mar 10, 2025

    • croc-ips

      Public
      0•1•0•0•Updated Mar 10, 2025Mar 10, 2025

    • pulp_soc

      Public
      pulp_soc is the core building component of PULP based SoCs
      riscvsystemverilogpulp
      Python
      •
      Other
      •81•79•5•6•Updated Mar 10, 2025Mar 10, 2025

    • eae-kws

      Public
      Python
      •
      Apache License 2.0
      •0•1•0•0•Updated Mar 8, 2025Mar 8, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •55•231•10•20•Updated Mar 6, 2025Mar 6, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•135•7•1•Updated Mar 4, 2025Mar 4, 2025

    • chimera-sdk

      Public
      C
      •
      Apache License 2.0
      •4•3•7•4•Updated Mar 4, 2025Mar 4, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •738•19•0•5•Updated Mar 3, 2025Mar 3, 2025

    • picobello

      Public
      whatever it means
      SystemVerilog
      •
      Other
      •0•5•7•0•Updated Feb 28, 2025Feb 28, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •31•181•15•5•Updated Feb 28, 2025Feb 28, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •157•585•31•9•Updated Feb 28, 2025Feb 28, 2025