This repository contains the material for the 13-week course 02118 - Introduction to Chip Design at the Technical University of Denmark (DTU). This course was developed with support from the Edu4Chip project.
This README file contains all the information related to the course. Please read it carefully to have an idea of the course structure and expectations.
- Practicalities
- Course Aim
- Reading Material
- Lecture Plan
- Project
- Exam
- Learning Objectives
- License
- Funding
Note: The first regular version will be given in Spring 2026. In Spring 2025, the course will be held in a flexible style (like a special course). Specifically, the content will be adapted to the students' needs and interests. Students are expected to contribute to the course actively and help improve the material for the future version of the course.
The course runs on Wednesdays from 13:00 to 17:00 in Building 308 - Room 017.
Each weekly session consist of a lecture and laboratory work. Some session will be fully dedicated to laboratory work (especially at the end of the course when you are expected to work on your project).
The course has two teachers:
You are very welcome to seek for help by approaching the teachers during the letctures and laboratory sessions, or via mail, or our Discord channel. Also, feedback about the course is much appreciated.
Install the OpenLane2 tools locally or use the server chipdesign1.compute.dtu.dk. The tools are currently usable on Linux and MacOS (even native with Mac Silicon). For Windows use WSL2 to have a Linux environment. There is no official support for Windows available. See Lab 1 for installation instructions.
This course is an introduction to the design of digital integrated circuits. It covers the basics of digital circuits, the tools used, and the process of designing a chip. The course is based open-source tools and open-source PDKs. The course also gives the possibility for student projects to be taped out on Tiny Tapeout.
- Lecture slides and lab material
- The textbook CMOS VLSI Design, A Circuits and Systems Perspective by Neil H. E. Weste and David Harris, also available as PDF
- The material related to the open-source tools we use, including installation instructions: OpenLean 2 Documentation
- For a quick start: OpenLane 2 in the browser, link is from efabless
- Caravel Documentation
- Chisel Book (as reference when doing designs in Chisel)
This is a tentative list of lectures. The course will be adapted to the students' needs and interests.
- Overview of chip design and its importance in modern electronics
- Basic terminology and concepts
- Covering the process (first intro in tool flow)
- AISC with standard cells
- PDK
- Edu4Chip
- Open Source tools (local) installation
- Running a "Hello World" example
- Exploring a standard gate
- See Lab 1 for instructions
- Lecture slides (also available as PDF in DTU-Learn)
- Weste and Harris: 1.1 and 1.12
- OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain
- Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper
- Tiny Tapeout: A Shared Silicon Tapeout Platform Accessible To Everyone
- The need for a controlled switch
- A brief history of the transistor
- The MOSFET transistor
- The NMOS inverter
- The CMOS inverter
- Other gates
- SiliWiz exercises
- See Lab 2 for instructions
- Lecture slides (also available as PDF in DTU-Learn)
- From the textbook:
- 1.3
- 1.4.1, 1.4.2, 1.4.3, 1.4.4, 1.4.5
- 1.5.1, 1.5.2
- 2.1, 2.2*, 2.3*
* quick read, no need to go into details with formulas
- Introduction to Verilog
- Introduction to Tiny Tapeout
- Small Verilog example (programmable counter)
- Write a testbench and run it on post-synthesis
- Do it in Chisel and in Verilog
- Do local hardening
- Simulate post-synthesis
- probably need a Verilog or cocotb testbench
- Explore Tiny Tapeout with a Verilog project (GitHub based)
- Use the counters in a memory mapped device (maybe)
- See Lab 3 for instructions
- Lecture slides (also available as PDF in DTU-Learn)
- Find good Verilog projects and read the code
- E.g., YARVI
- Introduction to the OpenLane2 ASIC design flow
- Input preparation and RTL linting
- Synthesis and logic optimization
- Floorplanning and placement
- Clock tree synthesis
- Routing and RC extraction
- Timing signoff and GDSII streaming
- Physical signoff and SDF simulation
- Overview of the course project and group formation
- Discussion about the project
- Form and register groups for the course project
- Choose a project component to work on (CPU, memory, peripherals, testing, etc.)
- Set up the development environment
- Start working on initial design steps
- Register groups in DTU-Learn and sign up in the GitHub repository
- Lecture slides (also available as PDF in DTU-Learn)
- OpenLane2 Documentation
This is a large documentation from whih this slide set is based upon, you do not need to read it all. Reference to it when needed.
- Lecture slides sources
- PDF in DTU Learn (05_Chisel_unit1-4)
- High paced introduction of Chisel
- Lab 1-4 at chisel-lab
- Work on the project
- Lecture slides
- Digital Design with Chisel
- System-on-Chip
- Interconnects
- Networks-on-Chip overview
- Work on the project
- Lecture slides (also available as PDF in DTU-Learn)
Each group presents their project plan and initial developments. This is a key milestone in the course, where you will receive valuable feedback from the teachers and your peers.
Please prepare a short presentation (a few simple slides) for a maximum duration of 10 minutes. Your presentation should include:
- Objectives: What are the key goals of your project?
- Current actions: What steps have been taken so far?
- Time plan: Timeline for development and key milestones.
- Preliminary design: Initial architecture, block diagrams, ideas, etc.
- Implementation and verification plan: How do you plan to implement and validate your design?
- Obstacles and open matters: Are there any obstacles or current problems that prevent moving forward?
After each presentation, we will have a 5 minutes feedback session.
The schedule of the presentations is announced on DTU-Learn. Please note that all groups should be present for all the presentations.
To make the most of the presentation and feedback session, please take into account the following tips:
- Keep your presentation structured and concise.
- Focus on clarity: explain your choices and reasoning.
- Be prepared to engage with feedback and questions.
- Work on the project
- Introduction to verification
- Verification methodologies
- Simulation-based verification
- Testbench design
- Assertions and coverage metrics
- Brief overview of formal verification
- Industry Standards, tools, and frameworks in verification
- Work on the project
- Lecture slides (also available as PDF in DTU-Learn)
- TBA
- Introduction to standard cells
- Role of standard cells in digital design
- Components of a standard cell library
- Types of standard cells (e.g., logic gates, flip-flops)
- Power, performance, and area
- Characterization of standard cells
- Memory types and memory organization
- Register files: FF, sync mem, latches, custom design
- Memory macros (IP blocks)
- Memory with the SkyWater PDK
- Models and simulation
- Work on the project
- Lecture slides - not yet availble
- Chip design rules
- Power distribution design, optimization, and analysis
- Digital design timing
- Clock distribution challenges and clock trees
- Power optimization through clock gating
- Timing closure
- Work on the project
- Chip design at Demant
- Industrial design and implementation flow overview
- Design and implementation considerations for low power
- Challenges in lower design nodes (and/or at lower voltages)
- Work on the project
- None
The full time slot is dedicated to project work.
- Work on the project
Each group presents their finalized project and discusses the results.
The course project is focused on designing and implementing a System-on-Chip (SoC) using open-source tools. The goal is to collaboratively develop a working SoC that includes a CPU, memory, peripherals, and essential interfaces.
The project is hosted at DTU-SoC-2025.
The project should be carried out in groups of 3 people (groups of 2 are also possible but less preferred). You are free to select your group members. Groups should be registered as soon as formed in the DTU-Learn group forming facility. If you experience difficulties forming a group, please contact the teacher.
When forming a new group, please make sure that you align expectations between the members. To achieve this, we recommend having a discussion about each member’s availability, work habits, and goals for the course to ensure a smooth and collaborative experience.
Each student group will contribute to a part of the SoC. You can choose from the following components:
- Cache system for Wildcat
- Memory controller (handling SPI-based flash, RAM access, memory-mapped peripherals)
- Peripherals:
- VGA character display
- Keyboard interface
- Serial port (UART)
- GPIO and timer
- Special IOs (PWM and others)
- SPI interface (with optional quad-mode support)
- Continuous integration (managing continuous verification after design changes)
- Verification (creating testbenches, simulations, and FPGA testing)
- Physical design tools (OpenLane2 workflow, synthesis, placement, routing, signoff)
- Caravel integration (integrating the design with the Caravel framework)
See Lecture 4 for more details.
To ensure smooth progress, we will coordinate weekly during the lab sessions. These sessions will be used to:
- Discuss progress and challenges faced by each group
- Provide feedback and guidance on design, implementation, and verification
- Address any issues related to tools and integration
- Keep track of milestones and ensure alignment with the tapeout schedule
- Work on the project
You are expected to hand-in a report describing your desing and your work. The report should be formatted as IEEE paper (IEEEtran template) and not be longer than 4 pages. In the following, you can find the expected content of the report (not all entries may apply to your project):
- Title
- Group number
- Names and student IDs of the group members
- Contributions: Clearly state what each team member contributed to the project. This section is crucial for evaluating individual contributions and ensuring fair grading.
- Introduction: Introduce your chosen design, outlining its purpose, objectives, and specifications.
- Design: Summarize the key aspects of your design, including its functionality and features. Provide a detailed block diagram to illustrate the overall architecture. Explain how the design fits into the larger system.
- Implementation:
- Describe how you implemented your design using Verilog, Chisel, or both.
- Highlight specific steps in the chip design process and explain how open-source tools were used.
- Include details on performance, and area and any challenges encountered during the implementation.
- Explain the testing methodology, including simulation results.
- Describe how you verified the design.
- Include results from DRC (Design Rule Check), timing analysis, etc. to demonstrate the design's readiness for tapeout.
- Tapeout preparation: Summarize the final steps taken to prepare the design for tapeout, (integration with the Caravel framework and/or and ensuring compliance with Tiny Tapeout requirements).
- Link/explanantion where to find your code Explain where your code is located in your repository. Possibly link to a README file that includes all needed technical instructions.
The deadline for the hand-in is the 4th of May 2025 at 23:59.
- Relevance and complexity
- Does the design address a meaningful challenge?
- Correctness
- Does the implementation function as intended?
- Are there any critical design flaws?
- Optimization
- Area and performance efficiency considerations
- Power consumption and design trade-offs
- Verification quality
- Comprehensive testbenches and accurate simulations
- Pre-synthesis and post-synthesis validation
- Testing quality
- Functional FPGA testing
- DRC and layout verification
- Completion
- Is the design ready for tapeout?
- Report quality
- Clear documentation of methodology, challenges, and results
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Week 4: Form groups, select project, open discussion
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Week 6: Finalize desing concept, define specs, align between groups
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Weeks 7-11: Develop design, run simulations, initiate physical design
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Weeks 12-13: Finalize physical design, complete DRC/LVS checks, prepare for submission
-
We could finish earlier for the April tapeout
Project report and presentation.
A student who has met the objectives of the course will be able to:
- Explain the physics and operation of semiconductor devices, including transistors, and be able to use this knowledge to design simple analog and digital circuits.
- Explain the fundamentals of memory design, including different types of memories and their organization, and be able to design and analyze memory subsystems.
- Explain the principles of SoC design, including partitioning, floor planning, and individual hardening, and be able to apply these principles to the design of a simple SoC.
- Explain the principles of multicore SoC design, including the use of NoCs and accelerators, and be able to apply these principles to the design of a simple multicore SoC.
- Explain the principles of verification in hardware design, including the use of agile hardware design techniques, and be able to apply these principles to the verification of a simple SoC design.
- Explain the tool flow involved in chip design, including the use of open-source tools, and be able to use these tools to design and simulate a simple SoC.
- Gain practical experience in the design and simulation of a simple SoC, and experience a virtual tapeout process.
- Develop critical thinking and problem-solving skills through the design and analysis of complex digital systems.
- Develop effective communication skills, including the ability to present and discuss technical ideas and designs, both orally and in writing.
All original content in this repository, including text, code, and other materials, is licensed under the CC0 1.0 Universal license (see LICENSE file), unless otherwise noted.
Certain images in this repository are not covered by the CC0 license. These images may be subject to more restrictive copyright terms. Where applicable, copyright and licensing information is provided for these images in the relevant directories, file descriptions, or as text integrated in the images.
Funded by the European Union within the Edu4Chip - Joint Education for Advanced Chip Design in Europe project. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or European Health and Digital Executive Agency (HaDEA). Neither the European Union nor the granting authority can be held responsible for them.
