- Develop FPGA logic in your browser!
- Run on your own FPGA!
- Share with others!
This document introduces the Virtual FPGA Lab. Separate documents will help you with:
- FPGA training using this platform
- Exporting to your FPGA board (if supported)
- TL-Verilog info: for humans for LLMs
New to FPGAs? Field-programmable gate arrays (FPGAs) are hardware circuits that can be programmed to carry out logical operations. They provide a sweet spot between implementing algorithms in software and fabricating application-specific integrated circuits (ASICs). They generally provide far better performance and power-efficiency than software implementations, and they require far less time and expense to implement than ASICs. They can be reprogrammed as needed to upgrade functionality or fix bugs, even after deployment to customers (in the "field"). FPGAs are also beneficial for prototyping application-specific integrated circuits (ASICs) or processors.
Though far more accessible than ASICs, FPGAs can still be a bit costly and difficult to learn for beginners and students. That's where this project comes in... and it's not just for beginners.
This project builds on all the power and ease-of-use of Makerchip IDE and adds convenience for FPGA development. In particular, we take advantage of Makerchip's Visual Debug feature to provide visualizations of FPGAs and their peripherals, thereby mimicking the physical lab experience. But better than the physical experience, you also have the benefits of simulation-based development: fast compilation (no synthesis, place-and-route, and bitstreams), full visibility of all signal values, and full control of time.
Makerchip further simplifies the experience with support for TL-Verilog in addition to Verilog/SystemVerilog. TL-Verilog features are more approachable to newcomers (not to mention the myriad benefits for experts).
In summary:
- Easy learning: Online; no board/peripherals required (but supported); simplified by TL-Verilog and Makerchip.
- Powerful for experts: (for open-source development) The virtual lab augments vendor tools with the benefits of Makerchip development and virtual FPGA board/peripheral integration.
- Vendor-agnostic: You're designs work on any FPGA boards with compatible peripherals. (Though currently-supported boards are all Xilinx-based.)
- Exportable: Code in Virtual Lab works on real FPGAs!!!
- Open Source: MIT-licensed.
- Zedboard Zynq-7000 ARM/FPGA SoC Development Board (Product Link)
- EDGE Artix 7 FPGA Development Board (Product Link)
- Basys 3 Artix-7 FPGA Trainer Board (Product Link)
- Icebreaker FPGA (Product Link)
- Nexys A7 (Product Link)
- CLEAR (Article) (no physical FPGA flow)
- Tiny Tapeout Evaluation Board (See Tiny Tapeout)
Currently we demonstrate using only these boards and we plan to add more boards in the future. You can very easily add your own FPGA boards. Contributions are welcome.
For simulation-based development, just click here, and go! (Right-click to open in a new tab.) Instructions below will guide you.
You can also start from any of the example project here.
For deployment to an FPGA, clone this repository or any other repository that uses this virtual lab, and copy an example or starting-point (TL-)Verilog template and open it from the Makerchip "Project" menu for editing with autosave.
Once you have some logic running in simulation, you'll be able to export your design to any supported physical FPGA board using these instructions.
\m5_TLV_version 1d: tl-x.org
\m5
use(m5-1.0)
\SV
m4_include_lib(['https://raw.githubusercontent.com/BalaDhinesh/Virtual-FPGA-Lab/main/tlv_lib/fpga_includes.tlv'])
m5_lab()
// ... SystemVerilog or TL-Verilog FPGA logic goes here ...
\TLV
/board
// Board selection:
// 0 m5_FIRST_CLAAS_ID
// 1 m5_ZEDBOARD_ID
// 2 m5_ARTIX7_ID
// 3 m5_BASYS3_ID
// 4 m5_ICEBREAKER_ID
// 5 m5_NEXYS_ID
// 6 m5_CLEAR_ID
m5+board(/board, /fpga, 3, *) // 3rd arg selects the board.
\SV
endmodule
The m5+board(...) macro (and peripheral macros, such as m5+lcd(...), define the hardware).
m5_lab() provides a superset of signals for I/Os. Those that have corresponding components on the board or peripherals should be driven/used. These include:
logic [15:0] led; // corresponding LEDs are lit when asserted
logic [6:0] sseg_segment_n; // corresponding segments are lit for selected digit(s) when deasserted
logic sseg_decimal_point_n; // decimal point is lit for selected digit(s) when deasserted
logic [7:0] sseg_digit_n; // corresponding digits are enabled when deasserted
You can see these signal declarations in the one-line expansion of the m5_lab() macro instantiation in the NAV-TLV tab.
In the starting template, the 3rd argument below can be used to select the board:
// Board selection:
// 0 - 1st CLaaS on AWS F1
// 1 - Zedboard
// 2 - Artix-7
// 3 - Basys3
// 4 - Icebreaker
// 5 - Nexys
// 6 - CLEAR
m5+board(/board, /fpga, 3, *) // 3rd arg selects the board.
Boards contain a subset of the following components,
// Internal to FPGA - no need to instantiate
// Signals:
// *led - led signal
// Internal to FPGA - no need to instantiate
// Signals:
// *sseg_digit_n - common anode signal
// *sseg_segment_n - seven segments
// *sseg_decimal_point_n - decimal point
// Internal to FPGA - no need to instantiate
// Signals:
// *push - push button signal
// Internal to FPGA - no need to instantiate
// Signals:
// *slideswitch - switch signal
// External to FPGA - instantiated using
m5+fpga_lcd()
// Signals:
// *out - 8-bit data/command line
// *lcd_enable - lcd enable signal
// *lcd_reset - lcd reset signal, 0 for command and 1 for data
// External to FPGA - instantiated using, e.g.
m5+fpga_vga(/board, 32)
// Signals:
// *vga_hsync - horizontal sync
// *vga_vsync - vertical sync
// *vga_r - red signal
// *vga_g - green signal
// *vga_b - blue signal
External and other peripherals can be instantiated using m5+ macros.
Here are some example you can load in Makerchip. You'll find the source code in this repository under examples. (Right-click links to open in a new tab.)
Board definitions appear at the top of the fpga_includes.tlv file. It should be easy
enough to interpret these parameters and add new boards by example. Be sure also to update all listings of available boards (which you can find using git grep -i zedboard).
The above steps update the virtual environment only. The physical FPGA build flow is a different matter and is platform-dependent, though open-source platform-agnostic build flows are available, and we'd love to use them.
We welcome your contributions.
Makerchip's Visual Debug feature is used to create the Virtual FPGA Lab.
You can also use Visual Deubg to visualize the logic running inside the FPGA.
By structuring your code to define your FPGA logic in TL-Verilog (which does not preclude using pure Verilog/SystemVerilog), you can add visualization to your logic.
Here's a sample code structure.
...
\SV
5_lab()
\TLV my_fpga_logic(/_fpga)
// ... Your TL-Verilog FPGA logic along with it's visualization ...
\TLV
/board
m5+board(/board, /fpga, 3, *, , my_fpga_logic)
...
Visual Debug documentation and examples can be found within the Makerchip IDE.
Detailed step-by-step instructions are provided in this link. (Credit to Mayank Kabra.)
LED Demo: Link
- To support more FPGA boards and peripherals.
- The automated shell script that converts TL-V code to run in an actual FPGA currently supports only Xilinx boards with Vivado software. So to provide scripts that target other vendors as well using open source tools. It would probably be wise to use EDAlize.
In our efforts, we've come across the following related projects. (Appearance on this list is not an endorsement, just a recognition that we are not alone.) Give us a pull request with any others.
- FPGA View A tracefile-driven virtual FPGA lab with touch UI for iPad initially, by Martin Fink
- A remote virtual FPGA lab environment providing multi-user access to each FPGA, by Alexander Magyari.
- Web FPGA A crowd-funded project to provide browser access to a local FPGA via WebUSB. Very cool, though it seems browsers have been removing support for WebUSB for security reasons.
- Labs Land A commercial option for virtualized labs.
This work has been sponsored through the OSFPGA Foundation and Google Summer of Code (GSoC) 2021(with the Free and Open Source Silicon Foundation (FOSSi) as a GSoC umbrella organization), with mentorship from Redwood EDA, LLC, and with training support from VLSI System Design.
- Akos Hadnagy, Primary Mentor
- Steve Hoover, Mentor; Founder & CEO, Redwood EDA, LLC
- Dylan McNamee, Advisor
- Bala Dhinesh, Contributing as a participant in Google Summer of Code 2021.
- Shivani Shah, Student at the International Institute of Information Technology, Bangalore
- Mayank Kabra, Student at the International Institute of Information Technology, Bangalore
Contributions are what make the open source community such an amazing vehicle to learn, inspire, and create. Any contributions you make are greatly appreciated. Kudos for filing bugs. Deepest thanks for fixing them and for contributing new features and support for new boards.
Distributed under the MIT License. See LICENSE.md.