These wrappers wrap the Xilinx Parametrized Macros for the SUS Hardware Design Language. These provide ROMs, RAMs, and FIFOs. By using these macros you can reliably synthesize to specific BRAM, URAM and URAM-FIFO resources. Currently as SUS only supports a single clock, only wrappers for single-clock modules are provided.
Important to know: Despite some memory primitives having LATENCY parameters, the absolute latencies on the ports are all set to '0. This is due to the presence of the enable signal. Use a LatencyOffset to get it back to the proper latency if desired.
Include Vivado2024.1/xpm_wrappers.sus in your sus project. You do not need to include any IPs in your project. Vivado already includes these natively.
To update these wrappers, you can re-run the code generator
python3 codegen_extern.py $XILINX_VIVADO/data/ip/xpm --all --filter xmp_list_supported.txt -o xpm_wrappers.sus