Skip to content

Commit

Permalink
aaa
Browse files Browse the repository at this point in the history
  • Loading branch information
@philiprbrenan
philiprbrenan committed Feb 10, 2025
1 parent 3250017 commit cc69940
Show file tree
Hide file tree
Showing 143 changed files with 406,453 additions and 433,072 deletions.
46 changes: 23 additions & 23 deletions BtreePA.java
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3529,7 +3529,7 @@ private static void test_verilog_delete() //
1,2=1 4=3 5,6=4 7=7 8,9=2 |
""");

t.runVerilogDeleteTest(4, 5, 386, """
t.runVerilogDeleteTest(4, 5, 381, """
6 |
0 |
5 |
Expand All @@ -3541,23 +3541,23 @@ private static void test_verilog_delete() //
1,2=1 5,6=4 7=7 8,9=2 |
""");

t.runVerilogDeleteTest(2, 7, 394, """
t.runVerilogDeleteTest(2, 7, 384, """
4 6 7 |
0 0.1 0.2 |
1 4 7 |
2 |
1=1 5,6=4 7=7 8,9=2 |
""");

t.runVerilogDeleteTest(1, 8, 314, """
t.runVerilogDeleteTest(1, 8, 309, """
6 7 |
0 0.1 |
1 7 |
2 |
5,6=1 7=7 8,9=2 |
""");

t.runVerilogDeleteTest(5, 4, 200, """
t.runVerilogDeleteTest(5, 4, 195, """
7 |
0 |
1 |
Expand All @@ -3573,7 +3573,7 @@ private static void test_verilog_delete() //
7=1 8,9=2 |
""");

t.runVerilogDeleteTest(7, 2, 234, """
t.runVerilogDeleteTest(7, 2, 224, """
8,9=0 |
""");

Expand Down Expand Up @@ -3615,47 +3615,47 @@ private static void test_verilog_put() //
1,2=0 |
""");
// Split instruction
t.runVerilogPutTest(3, 133, """
t.runVerilogPutTest(3, 127, """
1 |
0 |
1 |
2 |
1=1 2,3=2 |
""");

t.runVerilogPutTest(4, 255, """
t.runVerilogPutTest(4, 246, """
2 |
0 |
1 |
2 |
1,2=1 3,4=2 |
""");

t.runVerilogPutTest(5, 302, """
t.runVerilogPutTest(5, 298, """
2 3 |
0 0.1 |
1 3 |
2 |
1,2=1 3=3 4,5=2 |
""");

t.runVerilogPutTest(6, 328, """
t.runVerilogPutTest(6, 319, """
2 4 |
0 0.1 |
1 3 |
2 |
1,2=1 3,4=3 5,6=2 |
""");

t.runVerilogPutTest(7, 375, """
t.runVerilogPutTest(7, 371, """
2 4 5 |
0 0.1 0.2 |
1 3 4 |
2 |
1,2=1 3,4=3 5=4 6,7=2 |
""");

t.runVerilogPutTest(8, 482, """
t.runVerilogPutTest(8, 467, """
4 |
0 |
5 |
Expand All @@ -3667,7 +3667,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=2 |
""");

t.runVerilogPutTest(9, 437, """
t.runVerilogPutTest(9, 433, """
4 |
0 |
5 |
Expand All @@ -3679,7 +3679,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7=7 8,9=2 |
""");

t.runVerilogPutTest(10, 463, """
t.runVerilogPutTest(10, 454, """
4 |
0 |
5 |
Expand All @@ -3691,7 +3691,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=2 |
""");

t.runVerilogPutTest(11, 510, """
t.runVerilogPutTest(11, 506, """
4 |
0 |
5 |
Expand All @@ -3703,7 +3703,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9=8 10,11=2 |
""");

t.runVerilogPutTest(12, 454, """
t.runVerilogPutTest(12, 436, """
8 |
0 |
5 |
Expand All @@ -3715,7 +3715,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=8 11,12=2 |
""");

t.runVerilogPutTest(13, 437, """
t.runVerilogPutTest(13, 433, """
8 |
0 |
5 |
Expand All @@ -3727,7 +3727,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=8 11=10 12,13=2 |
""");

t.runVerilogPutTest(14, 463, """
t.runVerilogPutTest(14, 454, """
8 |
0 |
5 |
Expand All @@ -3739,7 +3739,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=8 11,12=10 13,14=2 |
""");

t.runVerilogPutTest(15, 510, """
t.runVerilogPutTest(15, 506, """
8 |
0 |
5 |
Expand All @@ -3751,7 +3751,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=8 11,12=10 13=9 14,15=2 |
""");

t.runVerilogPutTest(16, 496, """
t.runVerilogPutTest(16, 483, """
8 12 |
0 0.1 |
5 11 |
Expand All @@ -3763,7 +3763,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=8 11,12=10 13,14=9 15,16=2 |
""");

t.runVerilogPutTest(17, 502, """
t.runVerilogPutTest(17, 498, """
8 12 |
0 0.1 |
5 11 |
Expand All @@ -3775,7 +3775,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=8 11,12=10 13,14=9 15=12 16,17=2 |
""");

t.runVerilogPutTest(18, 528, """
t.runVerilogPutTest(18, 519, """
8 12 |
0 0.1 |
5 11 |
Expand All @@ -3787,7 +3787,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=8 11,12=10 13,14=9 15,16=12 17,18=2 |
""");

t.runVerilogPutTest(19, 575, """
t.runVerilogPutTest(19, 571, """
8 12 |
0 0.1 |
5 11 |
Expand All @@ -3799,7 +3799,7 @@ private static void test_verilog_put() //
1,2=1 3,4=3 5,6=4 7,8=7 9,10=8 11,12=10 13,14=9 15,16=12 17=13 18,19=2 |
""");

t.runVerilogPutTest(20, 527, """
t.runVerilogPutTest(20, 509, """
8 16 |
0 0.1 |
5 11 |
Expand Down
Loading

0 comments on commit cc69940

Please sign in to comment.