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AGNi MIUI-ST v5.7 stable [5.4.272]
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add a 90Hz only display variant
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@psndna88
psndna88 committed Mar 30, 2024
1 parent a0ce133 commit 532cd31
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4 changes: 2 additions & 2 deletions AGNi_version.sh
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KERNELDIR=`readlink -f .`

export AGNI_VERSION_PREFIX="stable"
export AGNI_VERSION="v5.6"
export AGNI_VERSION="v5.7"
sed -i 's/5.4.271/5.4.272/' $KERNELDIR/arch/arm64/configs/agni_*
sed -i 's/v5.5-stable/v5.6-stable/' $KERNELDIR/arch/arm64/configs/agni_*
sed -i 's/v5.6-stable/v5.7-stable/' $KERNELDIR/arch/arm64/configs/agni_*

echo " AGNi Version info loaded."

383 changes: 383 additions & 0 deletions arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-k11-38-08-0a-dsc-cmd_90hz.dtsi
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&mdss_mdp {
dsi_k11_38_08_0a_dsc_cmd: qcom,mdss_dsi_k11_38_08_0a_dsc_cmd {
qcom,mdss-dsi-panel-name = "xiaomi 38 08 0a cmd mode dsc dsi panel";
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
qcom,mdss-dsi-virtual-channel-id = <0>;
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-bpp = <24>;
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;

qcom,dsi-ctrl-num = <0>;
qcom,dsi-phy-num = <0>;

qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-lane-map = "lane_map_0123";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-lane-2-state;
qcom,mdss-dsi-lane-3-state;
qcom,mdss-dsi-dma-trigger = "trigger_sw";
qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-reset-sequence = <0 10>, <1 10>;
qcom,mdss-pan-physical-width-dimension = <695>;
qcom,mdss-pan-physical-height-dimension = <1546>;
qcom,mdss-dsi-te-pin-select = <1>;
qcom,mdss-dsi-wr-mem-start = <0x2c>;
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
qcom,mdss-dsi-te-dcs-command = <1>;
qcom,mdss-dsi-te-check-enable;
qcom,mdss-dsi-te-using-te-pin;
qcom,mdss-dsi-tx-eot-append;
qcom,mdss-dsi-lp11-init;

qcom,mdss-dsi-panel-mode-switch;

qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";

qcom,mdss-dsi-panel-hdr-enabled;
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
17000 15500 30000 8000 3000>;
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
qcom,mdss-dsi-panel-blackness-level = <3230>;
mi,panel-id = <0x4B3131 0x00380800>;
mi,hbm-51-ctl-flag;
mi,hbm-off-51-index = <1>;
mi,hbm-on-51-index = <1>;
mi,hbm-bl-min-level = <1>;
mi,hbm-bl-max-level = <2047>;
mi,max-brightness-clone = <8191>;
mi,thermal-dimming-flag;
mi,fp-display-on-optimize-flag;
mi,panel-hbm-backlight-threshold = <4095>;
mi,esd-err-irq-gpio = <&tlmm 75 8194>;
mi,panel-on-dimming-delay = <120>;
mi,mdss-dsi-panel-dc-threshold = <440>;
mi,mdss-dsi-panel-hbm-brightness = <1>;
qcom,dsi-select-clocks = "mux_byte_clk0","mux_pixel_clk0";
qcom,mdss-dsi-clk-strength = <101>;
qcom,panel-supply-entries = <33>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <2>;
qcom,mdss-dsi-bl-max-level = <2047>;
qcom,mdss-brightness-max-level = <2047>;
qcom,mdss-brightness-init-level = <2047>;
qcom,platform-te-gpio = <&tlmm 82 0>;
qcom,platform-reset-gpio = <&tlmm 24 0>;
phandle = <258>;

qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-cmd-mode;
qcom,mdss-dsi-panel-framerate = <90>;
qcom,mdss-dsi-panel-width = <1080>;
qcom,mdss-dsi-panel-height = <2400>;
qcom,mdss-dsi-h-front-porch = <16>;
qcom,mdss-dsi-h-back-porch = <8>;
qcom,mdss-dsi-h-pulse-width = <8>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <280>;
qcom,mdss-dsi-v-front-porch = <300>;
qcom,mdss-dsi-v-pulse-width = <16>;
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-panel-clockrate = <1100000000>;
qcom,mdss-dsi-panel-jitter = <0x5 0x1>;
qcom,mdss-mdp-transfer-time-us = <9500>;
qcom,mdss-dsi-on-command = [
/* 1 Sleep Out */
05 01 00 00 0A 00 02 11 00 /* Sleep Out */
/* 3 Common Setting */
/* 3.1 TE(Vsync) On/Off */
39 01 00 00 00 00 02 35 00 /* TE On(Vsync) */
/* DSC Setting */
39 01 00 00 00 00 02 9D 01 /* Compression Enable */
39 01 00 00 00 00 81 9E /* PPS Setting */
11 00 00 89 30 80 09 60
04 38 00 08 02 1C 02 1C
02 00 02 0E 00 20 00 BB
00 07 00 0C 0D B7 0C B7
18 00 10 F0 03 0C 20 00
06 0B 0B 33 0E 1C 2A 38
46 54 62 69 70 77 79 7B
7D 7E 01 02 01 00 09 40
09 BE 19 FC 19 FA 19 F8
1A 38 1A 78 1A B6 2A F6
2B 34 2B 74 3B 74 6B F4
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
/* 3.2 CASET/PASET Setting */
39 00 00 00 00 00 05 2A 00 00 04 37 /* CASET */
39 01 00 00 00 00 05 2B 00 00 09 5F /* PASET */
/* 3.3 11Bit Dimming Setting */
39 01 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 02 B0 01 /* Global para */
39 01 00 00 00 00 02 B7 4F /* 11Bit Dimming On*/
39 01 00 00 00 00 03 F0 A5 A5
/* 3.4 Err FG Setting*/
39 01 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 02 B0 02
39 00 00 00 00 00 05 EC 00 C2 C2 42
39 00 00 00 00 00 02 B0 0D
39 00 00 00 00 00 02 EC 19
39 00 00 00 00 00 02 B0 06
39 01 00 00 00 00 02 E4 10
39 01 00 00 00 00 03 F0 A5 A5
/* 3.5 Ripple improvement Setting*/
39 01 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 02 B0 36
39 00 00 00 00 00 02 D3 0F
39 01 00 00 00 00 02 F7 03
39 01 00 00 00 00 03 F0 A5 A5
/* 3.6 OFC (MIPI 1100Mbps/Lane, OSC 108.5Mhz)*/
39 01 00 00 00 00 03 F0 5A 5A
39 01 00 00 00 00 03 FC 5A 5A
39 00 00 00 00 00 02 B0 01
39 00 00 00 00 00 04 E4 A6 75 A3
39 01 00 00 00 00 0F E9 11 75 A6 75 A3 8D 06 20 8C A2 4E 00 32 32
39 01 00 00 00 00 03 FC A5 A5
39 01 00 00 00 00 03 F0 A5 A5
/* tsp_vsync tsp_hsync*/
39 01 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 04 DF 83 00 10
39 00 00 00 00 00 02 B0 01
39 01 00 00 00 00 02 E6 01
39 01 00 00 00 00 03 F0 A5 A5
/* flicker */
39 00 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 02 B0 08
39 00 00 00 00 00 02 D4 05
39 01 00 00 00 00 03 F0 A5 A5
/* 3.7 Hporch Setting */
39 01 00 00 00 00 03 F0 5A 5A
39 01 00 00 00 00 03 FC 5A 5A
39 00 00 00 00 00 02 B0 16
39 01 00 00 00 00 02 D1 6E
39 01 00 00 00 00 03 FC A5 A5
39 01 00 00 5A 00 03 F0 A5 A5
/* Dimming Setting*/
39 01 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 02 B0 06
39 00 00 00 00 00 02 B7 20 /* Dimming Speed Setting : 0x20 : 32Frames*/
39 00 00 00 00 00 02 B0 05
39 01 00 00 00 00 02 B7 93 /* 0x93 : ELVSS DIM ON */
39 01 00 00 00 00 03 F0 A5 A5
39 00 00 00 00 00 02 53 20
39 01 00 00 00 00 03 51 00 00 /* Write Display Brightness */
/* 5 Display On */
05 01 00 00 00 00 02 29 00
/* 90hz Frequency Select*/
39 01 00 00 00 00 02 60 10];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
/* Default Frequency Setting */
39 01 00 00 00 00 02 53 20
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

qcom,mdss-dsi-timing-switch-command = [
39 00 00 00 00 00 02 60 10
39 00 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 03 FC 5A 5A
39 00 00 00 00 00 02 B0 16
39 00 00 00 00 00 02 D1 6E
39 00 00 00 00 00 03 FC A5 A5
39 01 00 00 09 00 03 F0 A5 A5];
qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode";

qcom,mdss-dsi-nolp-command = [
39 01 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 02 B0 0A
39 00 00 00 00 00 02 EE 06
39 00 00 00 00 00 02 B0 0B
39 00 00 00 00 00 03 D8 59 70
39 00 00 00 00 00 02 60 10
39 00 00 00 00 00 03 FC 5A 5A
39 00 00 00 00 00 02 B0 16
39 00 00 00 00 00 02 D1 6E
39 00 00 00 00 00 03 FC A5 A5
39 01 00 00 00 00 02 53 28
39 01 00 00 0C 00 03 F0 A5 A5
];
qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode";

qcom,compression-mode = "dsc";
qcom,mdss-dsc-slice-height = <8>;
qcom,mdss-dsc-slice-width = <540>;
qcom,mdss-dsc-slice-per-pkt = <2>;
qcom,mdss-dsc-bit-per-component = <8>;
qcom,mdss-dsc-bit-per-pixel = <8>;
qcom,mdss-dsc-block-prediction-enable;
mi,mdss-dsi-dimmingon-command = [39 01 00 00 00 00 02 53 28];
mi,mdss-dsi-dimmingon-command-state = "dsi_hs_mode";
mi,mdss-dsi-dimmingoff-command = [39 01 00 00 00 00 02 53 20];
mi,mdss-dsi-dimmingoff-command-state = "dsi_hs_mode";
mi,mdss-dsi-hbm-on-command = [
39 01 00 00 00 00 02 53 e8
39 01 00 00 00 00 03 51 00 00];
mi,mdss-dsi-hbm-off-command = [
39 01 00 00 00 00 02 53 28
39 01 00 00 00 00 03 51 07 ff];
mi,mdss-dsi-hbm-on-command-state = "dsi_lp_mode";
mi,mdss-dsi-hbm-off-command-state = "dsi_lp_mode";
mi,mdss-dsi-doze-hbm-command = [
05 01 00 00 00 00 02 28 00
39 00 00 00 00 00 03 f0 5a 5a
39 00 00 00 00 00 02 60 00
39 00 00 00 00 00 03 fc 5a 5a
39 00 00 00 00 00 02 b0 16
39 00 00 00 00 00 02 d1 2e
39 00 00 00 00 00 03 fc a5 a5
39 00 00 00 00 00 02 b0 0b
39 00 00 00 00 00 03 d8 50 00
39 00 00 00 00 00 02 53 22
39 01 00 00 22 00 03 f0 a5 a5
05 01 00 00 00 00 02 29 00];
mi,mdss-dsi-doze-lbm-command = [
05 01 00 00 00 00 02 28 00
39 00 00 00 00 00 03 f0 5a 5a
39 00 00 00 00 00 02 60 00
39 00 00 00 00 00 03 fc 5a 5a
39 00 00 00 00 00 02 b0 16
39 00 00 00 00 00 02 d1 2e
39 00 00 00 00 00 03 fc a5 a5
39 00 00 00 00 00 02 b0 0b
39 00 00 00 00 00 03 d8 50 00
39 00 00 00 00 00 02 53 23
39 01 00 00 22 00 03 f0 a5 a5
05 01 00 00 00 00 02 29 00];
mi,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode";
mi,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode";
mi,mdss-dsi-flat-mode-on-command = [
39 00 00 00 00 00 03 f0 5a 5a
39 00 00 00 00 00 03 c2 2d 27
39 00 00 00 00 00 02 f7 03
39 01 00 00 09 00 03 f0 a5 a5];
mi,mdss-dsi-flat-mode-off-command = [
39 00 00 00 00 00 03 f0 5a 5a
39 00 00 00 00 00 03 c2 2d 07
39 00 00 00 00 00 02 f7 03
39 01 00 00 09 00 03 f0 a5 a5];
mi,mdss-dsi-flat-mode-on-command-state = "dsi_lp_mode";
mi,mdss-dsi-flat-mode-off-command-state = "dsi_lp_mode";
mi,mdss-dsi-crc-off-command = [
39 01 00 00 00 00 02 81 00
39 00 00 00 00 00 03 f0 5a 5a
39 00 00 00 00 00 02 b1 01
39 01 00 00 00 00 03 f0 a5 a5];
mi,mdss-dsi-crc-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 19 09 0a 09 02 04 00 1e 0f];
qcom,display-topology = <0x01 0x01 0x01>;
qcom,default-topology-index = <0x00>;
};
};
};
};

&dsi_k11_38_08_0a_dsc_cmd {
mi,panel-id = <0x4B3131 0x00380800>;

mi,hbm-51-ctl-flag;
mi,hbm-off-51-index = <1>;
mi,hbm-on-51-index = <1>;
mi,hbm-bl-min-level = <1>;
mi,hbm-bl-max-level = <2047>;
mi,max-brightness-clone = <8191>;
mi,thermal-dimming-flag;
mi,fp-display-on-optimize-flag;

mi,esd-err-irq-gpio = <&tlmm 75 0x2002>;

mi,panel-on-dimming-delay = <120>;

mi,mdss-dsi-panel-dc-threshold = <440>;
mi,mdss-dsi-panel-hbm-brightness = <1>;

qcom,mdss-dsi-display-timings {
timing@0{
mi,mdss-dsi-dimmingon-command = [39 01 00 00 00 00 02 53 28];
mi,mdss-dsi-dimmingon-command-state = "dsi_hs_mode";
mi,mdss-dsi-dimmingoff-command = [39 01 00 00 00 00 02 53 20];
mi,mdss-dsi-dimmingoff-command-state = "dsi_hs_mode";

mi,mdss-dsi-hbm-on-command = [
39 01 00 00 00 00 02 53 E8
39 01 00 00 00 00 03 51 00 00
];
mi,mdss-dsi-hbm-off-command = [
39 01 00 00 00 00 02 53 28
39 01 00 00 00 00 03 51 07 FF
];
mi,mdss-dsi-hbm-on-command-state = "dsi_lp_mode";
mi,mdss-dsi-hbm-off-command-state = "dsi_lp_mode";

mi,mdss-dsi-doze-hbm-command = [
05 01 00 00 00 00 02 28 00
39 00 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 02 60 00
39 00 00 00 00 00 03 FC 5A 5A
39 00 00 00 00 00 02 B0 16
39 00 00 00 00 00 02 D1 2E
39 00 00 00 00 00 03 FC A5 A5
39 00 00 00 00 00 02 B0 0B
39 00 00 00 00 00 03 D8 50 00
39 00 00 00 00 00 02 53 22
39 01 00 00 22 00 03 F0 A5 A5
05 01 00 00 00 00 02 29 00
];
mi,mdss-dsi-doze-lbm-command = [
05 01 00 00 00 00 02 28 00
39 00 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 02 60 00
39 00 00 00 00 00 03 FC 5A 5A
39 00 00 00 00 00 02 B0 16
39 00 00 00 00 00 02 D1 2E
39 00 00 00 00 00 03 FC A5 A5
39 00 00 00 00 00 02 B0 0B
39 00 00 00 00 00 03 D8 50 00
39 00 00 00 00 00 02 53 23
39 01 00 00 22 00 03 F0 A5 A5
05 01 00 00 00 00 02 29 00
];
mi,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode";
mi,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode";

mi,mdss-dsi-flat-mode-on-command = [
39 00 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 03 C2 2D 27
39 00 00 00 00 00 02 F7 03
39 01 00 00 09 00 03 F0 A5 A5
];
mi,mdss-dsi-flat-mode-off-command = [
39 00 00 00 00 00 03 F0 5A 5A
39 00 00 00 00 00 03 C2 2D 07
39 00 00 00 00 00 02 F7 03
39 01 00 00 09 00 03 F0 A5 A5
];
mi,mdss-dsi-flat-mode-on-command-state = "dsi_lp_mode";
mi,mdss-dsi-flat-mode-off-command-state = "dsi_lp_mode";

mi,mdss-dsi-crc-off-command = [
/* CRC Disable (Normal mode) */
39 01 00 00 00 00 02 81 00
39 00 00 00 00 00 03 F0 5A 5A
/* CRC Bypass */
39 00 00 00 00 00 02 B1 01
39 01 00 00 00 00 03 F0 A5 A5
];
mi,mdss-dsi-crc-off-command-state = "dsi_hs_mode";
};
};
};

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