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[RV64_DYNAREC] Optimized AVX RVV support #4579

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Merged
ksco merged 12 commits into from
Oct 20, 2026
Merged

[RV64_DYNAREC] Optimized AVX RVV support #4579

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a443633
[RV64_DYNAREC] Added XMM/YMM preload support
ksco Oct 19, 2026
0ec3bda
[RV64_DYNAREC] Raised MXCSR invalid flag on overflow
ksco Oct 19, 2026
1376cff
[RV64_DYNAREC] Fixed YMM upper 128-bit writeback
ksco Oct 19, 2026
04130a9
[RV64_DYNAREC] Restricted AES vector path to 128-bit operands
ksco Oct 19, 2026
71fd14b
[RV64_DYNAREC] Kept vtype across linear instructions
ksco Oct 19, 2026
f4fcdc6
[RV64_DYNAREC] Forced vsetvli in SSE cache purge
ksco Oct 19, 2026
5757bdc
[RV64_DYNAREC] Used encoded registers for AVX vector operands
ksco Oct 19, 2026
967c5a0
[RV64_DYNAREC] Added combined VY/EY/GY vector load macros
ksco Oct 19, 2026
049d653
[RV64_DYNAREC] Fixed AVX source/destination aliasing
ksco Oct 19, 2026
d810b26
[RV64_DYNAREC] Used vl=1 RVV for scalar SSE/AVX opcodes
ksco Oct 19, 2026
a8d25a3
[RV64_DYNAREC] Used LMUL1 scratch for byte shuffles
ksco Oct 19, 2026
8f83e57
[RV64_DYNAREC] Deferred upper-zero and matched AVX load SEW
ksco Oct 19, 2026
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2 changes: 1 addition & 1 deletion src/dynarec/dynarec_arch.h
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Original file line number Diff line number Diff line change
Expand Up @@ -116,7 +116,7 @@ extern void la64_next_invalid();
#define RAZ_SPECIFIC(A, N)
#define UPDATE_SPECIFICS(A)
#define PREUPDATE_SPECIFICS(A) updateNativeFlags(A)
#define POSTUPDATE_SPECIFICS(A)
#define POSTUPDATE_SPECIFICS(A) updatePreloads(A)

#define ARCH_SIZE(A) get_size_arch(A)
#define ARCH_FILL(A, B, C) populate_arch(A, B, C)
Expand Down
4 changes: 3 additions & 1 deletion src/dynarec/dynarec_native_pass.c
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Expand Up @@ -192,6 +192,8 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
if(!ninst) {
if (BOX64DRENV(dynarec_callret) >= 2)
doEnterBlock(dyn, 0, x1, x2, x3);
if (dyn->insts[0].preload_xmmymm)
doPreload(dyn, 0);
}
#endif
fpu_propagate_stack(dyn, ninst);
Expand Down Expand Up @@ -333,7 +335,7 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
else if (is_opcode_volatile && dyn->insts[ninst].will_read)
DMB_ISHLD();
#endif
#if defined(ARM64) || defined(LA64)
#if defined(ARM64) || defined(LA64) || defined(RV64)
if(dyn->insts[ninst].x64.has_next && dyn->insts[ninst+1].preload_xmmymm) {
doPreload(dyn, ninst+1);
}
Expand Down
2 changes: 2 additions & 0 deletions src/dynarec/rv64/dynarec_rv64_0f.c
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Expand Up @@ -428,6 +428,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
FRFLAGS(x5); // get back FPSR to check the IOC bit
ANDI(x5, x5, (1 << FR_NV) | (1 << FR_OF));
BEQ_MARKi(x5, xZR, i);
emit_mxcsr_raise_invalid(x5);
MOV32w(x1, 0x80000000);
MARKi(i);
}
Expand All @@ -451,6 +452,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
FRFLAGS(x5); // get back FPSR to check the IOC bit
ANDI(x5, x5, (1 << FR_NV) | (1 << FR_OF));
BEQ_MARKi(x5, xZR, i);
emit_mxcsr_raise_invalid(x5);
MOV32w(x1, 0x80000000);
MARKi(i);
}
Expand Down
2 changes: 1 addition & 1 deletion src/dynarec/rv64/dynarec_rv64_0f_vector.c
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Expand Up @@ -1156,7 +1156,7 @@ uintptr_t dynarec64_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip,
GETGX_vector(v0, 1, VECTOR_SEW32);
GETEX_vector(v1, 0, 1, VECTOR_SEW32);
u8 = F8;
q0 = fpu_get_scratch(dyn);
q0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL1);
d0 = fpu_get_scratch(dyn);
d1 = fpu_get_scratch(dyn);
if (cpuext.xtheadvector) { // lack of vrgatherei16.vv
Expand Down
3 changes: 3 additions & 0 deletions src/dynarec/rv64/dynarec_rv64_660f.c
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Expand Up @@ -209,6 +209,7 @@ uintptr_t dynarec64_660F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
FRFLAGS(x5); // get back FPSR to check the IOC bit
ANDI(x5, x5, (1 << FR_NV) | (1 << FR_OF));
BEQ_MARKi(x5, xZR, i);
emit_mxcsr_raise_invalid(x5);
MOV32w(x1, 0x80000000);
MARKi(i);
}
Expand All @@ -232,6 +233,7 @@ uintptr_t dynarec64_660F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
FRFLAGS(x5); // get back FPSR to check the IOC bit
ANDI(x5, x5, (1 << FR_NV) | (1 << FR_OF));
BEQ_MARKi(x5, xZR, i);
emit_mxcsr_raise_invalid(x5);
MOV32w(x1, 0x80000000);
MARKi(i);
}
Expand Down Expand Up @@ -2337,6 +2339,7 @@ uintptr_t dynarec64_660F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
FRFLAGS(x5); // get back FPSR to check the IOC bit
ANDI(x5, x5, (1 << FR_NV) | (1 << FR_OF));
BEQ_MARK(x5, xZR);
emit_mxcsr_raise_invalid(x5);
MOV32w(x3, 0x80000000);
MARK;
FSFLAGSI(0); // // reset all bits
Expand Down
2 changes: 1 addition & 1 deletion src/dynarec/rv64/dynarec_rv64_660f_vector.c
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Expand Up @@ -1525,7 +1525,7 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1);
GETEX_vector(q1, 0, 1, VECTOR_SEW64);
GETGX_empty_vector(q0);
v0 = fpu_get_scratch(dyn);
v0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL1);
tmp64u0 = F8;
if (cpuext.xtheadvector) { // lack of vrgatherei16.vv
v1 = fpu_get_scratch(dyn);
Expand Down
56 changes: 16 additions & 40 deletions src/dynarec/rv64/dynarec_rv64_avx_0f_vector.c
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Expand Up @@ -94,7 +94,7 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
INST_NAME("VMOVLPS Ex, Gx");
nextop = F8;
if (MODREG) return 0;
GETGY_vector_cached(q0, VECTOR_SEW64);
GETGY_vector(q0, VECTOR_SEW64);
addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 1, 0);
VMV_X_S(x4, q0);
SD(x4, ed, fixedaddress);
Expand All @@ -103,9 +103,7 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
case 0x14:
INST_NAME("VUNPCKLPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
q2 = fpu_get_scratch(dyn);
v1 = fpu_get_scratch(dyn);
v2 = fpu_get_scratch(dyn);
Expand All @@ -122,9 +120,7 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
case 0x15:
INST_NAME("VUNPCKHPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
q2 = fpu_get_scratch(dyn);
v1 = fpu_get_scratch(dyn);
v2 = fpu_get_scratch(dyn);
Expand Down Expand Up @@ -166,7 +162,7 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
INST_NAME("VMOVHPS Ex, Gx");
nextop = F8;
if (MODREG) return 0;
GETGY_vector_cached(q0, VECTOR_SEW64);
GETGY_vector(q0, VECTOR_SEW64);
q1 = fpu_get_scratch(dyn);
VSLIDEDOWN_VI(q1, q0, 1, VECTOR_UNMASKED);
VMV_X_S(x4, q1);
Expand Down Expand Up @@ -256,57 +252,45 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
case 0x54:
INST_NAME("VANDPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VAND_VV(v0, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, VECTOR_SEW32);
break;
case 0x55:
INST_NAME("VANDNPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector_safe(v0, q0, q1, VECTOR_SEW32);
VXOR_VI(v0, q0, 0x1f, VECTOR_UNMASKED);
VAND_VV(v0, v0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, VECTOR_SEW32);
break;
case 0x56:
INST_NAME("VORPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VOR_VV(v0, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, VECTOR_SEW32);
break;
case 0x57:
INST_NAME("VXORPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VXOR_VV(v0, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, VECTOR_SEW32);
break;
case 0x58:
if (!BOX64ENV(dynarec_fastnan)) return 0;
INST_NAME("VADDPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VFADD_VV(v0, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, VECTOR_SEW32);
break;
case 0x59:
if (!BOX64ENV(dynarec_fastnan)) return 0;
INST_NAME("VMULPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VFMUL_VV(v0, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, VECTOR_SEW32);
break;
Expand Down Expand Up @@ -345,18 +329,14 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
if (!BOX64ENV(dynarec_fastnan)) return 0;
INST_NAME("VSUBPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VFSUB_VV(v0, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, VECTOR_SEW32);
break;
case 0x5D:
INST_NAME("VMINPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VMFLT_VV(VMASK, q0, q1, VECTOR_UNMASKED);
VMERGE_VVM(v0, q1, q0);
PUTGY_vector(v0, VECTOR_SEW32);
Expand All @@ -365,18 +345,14 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
if (!BOX64ENV(dynarec_fastnan)) return 0;
INST_NAME("VDIVPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VFDIV_VV(v0, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, VECTOR_SEW32);
break;
case 0x5F:
INST_NAME("VMAXPS Gx, Vx, Ex");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETEY_vector(q1, 0, VECTOR_SEW32);
GETGY_empty_vector(v0);
GETGY_empty_VYEY_vector(v0, q0, q1, VECTOR_SEW32);
VMFLT_VV(VMASK, q1, q0, VECTOR_UNMASKED);
VMERGE_VVM(v0, q1, q0);
PUTGY_vector(v0, VECTOR_SEW32);
Expand Down Expand Up @@ -465,7 +441,7 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
case 0xC2:
INST_NAME("VCMPPS Gx, Vx, Ex, Ib");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETVY_vector(q0, VECTOR_SEW32);
GETEY_vector(q1, 1, VECTOR_SEW32);
u8 = F8;
GETGY_empty_vector(v0);
Expand Down Expand Up @@ -522,7 +498,7 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
case 0xC6:
INST_NAME("VSHUFPS Gx, Vx, Ex, Ib");
nextop = F8;
GETVY_vector_cached(q0, VECTOR_SEW32);
GETVY_vector(q0, VECTOR_SEW32);
GETEY_vector(q1, 1, VECTOR_SEW32);
u8 = F8;
selectors = 0;
Expand Down
10 changes: 5 additions & 5 deletions src/dynarec/rv64/dynarec_rv64_avx_66_0f38.c
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Expand Up @@ -2186,7 +2186,7 @@ uintptr_t dynarec64_AVX_66_0F38(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
case 0xDC:
INST_NAME("VAESENC Gx, Vx, Ex");
nextop = F8;
if (cpuext.zvkned && cpuext.vlen >= 32) {
if (cpuext.zvkned && cpuext.vlen >= 32 && !vex.l) {
gd = ((nextop & 0x38) >> 3) + (rex.r << 3);
SET_AVX_VECTOR_WIDTH(x1, VECTOR_SEW32);
v0 = fpu_get_scratch(dyn);
Expand Down Expand Up @@ -2258,7 +2258,7 @@ uintptr_t dynarec64_AVX_66_0F38(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
case 0xDD:
INST_NAME("VAESENCLAST Gx, Vx, Ex");
nextop = F8;
if (cpuext.zvkned && cpuext.vlen >= 32) {
if (cpuext.zvkned && cpuext.vlen >= 32 && !vex.l) {
gd = ((nextop & 0x38) >> 3) + (rex.r << 3);
SET_AVX_VECTOR_WIDTH(x1, VECTOR_SEW32);
v0 = fpu_get_scratch(dyn);
Expand Down Expand Up @@ -2333,7 +2333,7 @@ uintptr_t dynarec64_AVX_66_0F38(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
if (vex.l) {
DEFAULT;
}
if (cpuext.zvkned && cpuext.vlen >= 32) {
if (cpuext.zvkned && cpuext.vlen >= 32 && !vex.l) {
gd = ((nextop & 0x38) >> 3) + (rex.r << 3);
SET_AVX_VECTOR_WIDTH(x1, VECTOR_SEW32);
v1 = fpu_get_scratch(dyn);
Expand Down Expand Up @@ -2365,7 +2365,7 @@ uintptr_t dynarec64_AVX_66_0F38(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
case 0xDE:
INST_NAME("VAESDEC Gx, Vx, Ex");
nextop = F8;
if (cpuext.zvkned && cpuext.vlen >= 32) {
if (cpuext.zvkned && cpuext.vlen >= 32 && !vex.l) {
gd = ((nextop & 0x38) >> 3) + (rex.r << 3);
SET_AVX_VECTOR_WIDTH(x1, VECTOR_SEW32);
v0 = fpu_get_scratch(dyn);
Expand Down Expand Up @@ -2444,7 +2444,7 @@ uintptr_t dynarec64_AVX_66_0F38(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
case 0xDF:
INST_NAME("VAESDECLAST Gx, Vx, Ex");
nextop = F8;
if (cpuext.zvkned && cpuext.vlen >= 32) {
if (cpuext.zvkned && cpuext.vlen >= 32 && !vex.l) {
gd = ((nextop & 0x38) >> 3) + (rex.r << 3);
SET_AVX_VECTOR_WIDTH(x1, VECTOR_SEW32);
v0 = fpu_get_scratch(dyn);
Expand Down
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