v0.6.4

Added

• Add tracing support to inst64 #52.

Changed

• Various fixes and small changes to upstream PULPv2/Chimera features. Combining PRs #49, #55, #56, #57 in #66.
• Minor changes to fix linting #54.
• Expand tracer to track more signals, increase Verilator support #52.

Fixed

• Ensuring r_dp_valid_i is ready before accepting data #67.
• Updated upload-pages-artifact to v3 #68 and upload-artifact to v4 to restore CI.
• Fix DMCPY instruction in inst64 front-end for multi-channel DMA operation #65.
• Ensure correct PageAddrWidth in legalizer for transfers without bursts; fixes issue #53 and was merged as #53.

v0.6.3

0.6.3 - 2024-07-02

Added

• Multichannel support in inst64 #46

Fixed

• inst64 sources are only present if the snitch_cluster target is set #47.
• zero-length ND transfers are properly handled #50.

v0.6.2

Fixed

• Missing signal assign in backend template

v0.6.0

Changed

• Various cleanup and modernization passes: CI, documentation, scripts
• Rework ND-front-ends for both 32 and 64-bit systems #30,
  #32, #33
• Remove default system wrappers and drivers
• Update descriptor-based frontend #18,
  #26
• Update tracer to the multiprotocol version of iDMA #8
• Modified init protocol to support writes to implement the simple FIFO interface
• Update inst64 frontend, add changes from Occamy, and update to newest backend version
• Upstream resources and update dependencies

Added

• Add true multiprotocol capabilities to iDMA using MARIO #22
• Add multiple default protocols next to AXI read/write:
  • AXI read, OBI write
  • OBI read, AXI write
  • AXI and AXI Stream read/write
  • OBI read, AXI write, Init read/write
  • AXI read, OBI and Init read/write
• Add RT midend #24
• Add Mempool midend #34
• Add retarget.py Python script to transform patterns to new protocol configurations

v0.5.1

Fixed

• Increase SV language compatibility in dma_core_wrap. #28.

v0.5.0

0.5.0 - 2023-10-14

Changed

• Add a struct variant to CVA6's dma_core_wrap #25.
• Expose all important back-end parameters in dma_core_wrap #27.

Added

• Add a 2D version of the 64-bit register-based front-end intended to be used with CVA6 and enable
  it in the dma_core_wrap #27.

v0.4.2

0.4.2 - 2023-02-09

Fixed

• Fix idma_backend instantiation in dma_core_wrap #23.

v0.4.1

0.4.1 - 2023-02-08

Fixed

• Fix typo in dma_core_wrap #21.

v0.4.0

Changed

• Bump AXI version to v.0.39.0-beta.2 #20.
• Add new protocol capabilities introduced by #20 to the README.md.

Fixed

• Various fixes; add missing ports in the testbenches, remove stale comments, and remove duplicates in Bender.yml #17.

Added

• Add guard.svh, a simple macro to guard non synthesizable code in the iDMA repository #17.
• Add support for the OBI v1.5.0 protocol #20.
• Add support for the AXI4 Lite protocol #20.

v0.3.1

Fixed

• dma_core_wrap: Remove parameter DmaAddrWidth in idma_reg64_frontend. #16.