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Commit 97f8fff

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Andrea Belano
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[snitch] Fix typo and add xif performance counter
1 parent 65ab2a8 commit 97f8fff

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2 files changed

+14
-5
lines changed

2 files changed

+14
-5
lines changed

hw/snitch/src/snitch.sv

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
139139
localparam bit NSX = XF16 | XF16ALT | XF8 | XFVEC;
140140

141141
logic illegal_inst, illegal_csr;
142+
logic unsupported_xif_feature;
142143
logic interrupt, ecall, ebreak;
143144
logic zero_lsb;
144145

@@ -354,7 +355,6 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
354355
`FFAR(sb_q, sb_d, '0, clk_i, rst_i)
355356
`FFAR(fcsr_q, fcsr_d, '0, clk_i, rst_i)
356357

357-
// TODO(abelano) Should we add a performance counter for the XIF?
358358
// performance counter
359359
`ifdef SNITCH_ENABLE_PERF
360360
logic [63:0] cycle_q;
@@ -363,16 +363,19 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
363363
logic retired_load_q;
364364
logic retired_i_q;
365365
logic retired_acc_q;
366+
logic retired_x_q;
366367
`FFAR(cycle_q, cycle_q + 1, '0, clk_i, rst_i)
367368
`FFLAR(instret_q, instret_q + 1, !stall, '0, clk_i, rst_i)
368369
`FFAR(retired_instr_q, !stall, '0, clk_i, rst_i)
369370
`FFAR(retired_load_q, retire_load, '0, clk_i, rst_i)
370371
`FFAR(retired_i_q, retire_i, '0, clk_i, rst_i)
371372
`FFAR(retired_acc_q, retire_acc, '0, clk_i, rst_i)
373+
`FFAR(retired_x_q, retire_x, '0, clk_i, rst_i)
372374
assign core_events_o.retired_instr = retired_instr_q;
373375
assign core_events_o.retired_load = retired_load_q;
374376
assign core_events_o.retired_i = retired_i_q;
375377
assign core_events_o.retired_acc = retired_acc_q;
378+
assign core_events_o.retired_x = retired_x_q;
376379
`else
377380
assign core_events_o = '0;
378381
`endif
@@ -537,7 +540,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
537540
assign rd = inst_data_i[7 + RegWidth - 1:7];
538541
assign rs1 = inst_data_i[15 + RegWidth - 1:15];
539542
assign rs2 = inst_data_i[20 + RegWidth - 1:20];
540-
assign rs3 = inst_data_i[27 + RegWidth - 1:20];
543+
assign rs3 = inst_data_i[27 + RegWidth - 1:27];
541544

542545
always_comb begin
543546
illegal_inst = 1'b0;
@@ -549,7 +552,9 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
549552
opc_select = None;
550553

551554
x_issue_req_o = '0;
552-
x_issue_valid_o = '0;
555+
x_issue_valid_o = 1'b0;
556+
557+
unsupported_xif_feature = 1'b0;
553558

554559
flush_i_valid_o = 1'b0;
555560
tlb_flush = 1'b0;
@@ -2320,7 +2325,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
23202325
& ((itlb_valid & itlb_ready) | ~trans_active);
23212326

23222327
// Flag the instruction as illegal if not accepted by the coprocessor or if it requests an unsupported operation
2323-
illegal_inst = x_issue_ready_i & x_issue_valid_o & (~x_issue_resp_i.accept | |{x_issue_resp_i.dualwrite, x_issue_resp_i.dualread, x_issue_resp_i.loadstore, x_issue_resp_i.ecswrite});
2328+
illegal_inst = x_issue_ready_i & x_issue_valid_o & ~x_issue_resp_i.accept;
2329+
unsupported_xif_feature = x_issue_ready_i & x_issue_valid_o & |{x_issue_resp_i.dualwrite, x_issue_resp_i.dualread, x_issue_resp_i.loadstore, x_issue_resp_i.ecswrite};
23242330
end
23252331
endcase
23262332

@@ -2340,8 +2346,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
23402346
| ld_addr_misaligned
23412347
| st_addr_misaligned
23422348
| illegal_csr
2349+
| unsupported_xif_feature
23432350
| (dtlb_page_fault & dtlb_trans_valid)
2344-
| (itlb_page_fault & itlb_trans_valid);
2351+
| (itlb_page_fault & itlb_trans_valid)
2352+
| x_result_valid_i & (x_result_i.err | x_result_i.exc);
23452353

23462354
`ifndef VCS
23472355
// pragma translate_off

hw/snitch/src/snitch_pkg.sv

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,7 @@ package snitch_pkg;
172172
logic retired_load; // number of load instructions retired by the core
173173
logic retired_i; // number of base instructions retired by the core
174174
logic retired_acc; // number of offloaded instructions retired by the core
175+
logic retired_x; // number of offloaded instructions to the XIF retired by the core
175176
} core_events_t;
176177

177178
// SSRs

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