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fix(vector): reorganize vector tests and add new tests for vsetvli #1268
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Collaborator
adingank-qualcomm
commented
Dec 4, 2025
- start vset
- update vset
- start adding CSRs
- start adding CSRs
- add skeleton for remaining CSRs
- add skeleton for remaining CSRs
- update CSRs based on comments
- add remaining csr details
- update csr read in vset
- address comments
- add pretty tables in csr descriptions
- break up csr write fields in vset
- feat(idl): add constraints to IDL
- feat: add mock spec to udb gem for testing, add Condition classes
- docs: document schema conditions and idl implications
- refactor: move parameters into their own YAML files
- feat: wip
- feat: wip
- update vl assignment in ranged case
- add vxsat and vxrm sw_write
- set vill in unsupported cases
- fix idl compile errors
- adress dhower's feedback
- Update spec/std/isa/ext/V.yaml
- Update spec/std/isa/csr/V/vxsat.yaml
- Update spec/std/isa/csr/V/vxrm.yaml
- Update spec/std/isa/csr/V/vcsr.yaml
- Update spec/std/isa/inst/V/vsetivli.yaml
- adress thinkopenly's comments
- fix:(vector): restructuring vset instructions operation()
- chore: dependency update
- feat: wip
- fix: merge errors
- feat(vector): add rv32 vector configuration based on rv32-riscv-tests cfg
- wip
- feat(vector): add skeleton of vadd.vv
- wip
- add regress job dependency
- Fix path in regression for udb unit tests
- wip
- wip
- wip
- wip
- wip
- wip
- fix(vector): fix vset failures*
- wip
- wip
- wip
- wip
- wip
- feat(vector): add skeleton of vadd.vv
- fix(vector): fix vset failures*
- wip
- wip
- fix(vector): implement vadd.vv
- fix(vector): extract V parameters into their own files
- fix(vector): get iss through compilation after changes from issue 891
- fix(vector): add launch config for vsetvli debug
- fix(vector): sort param topologically w.r.t. dependence
- fix(vector): add 64 to SXLEN as a workaround to get ISS to run a test
- fix(vector): use const refs with std::find() in param_value() and defined()
- fix(vector): handle rs1==x0 case in vsetvli
- fix(vector): fix indentation in vsetvli
- feat: infrastructure to extend the riscv-tests suite without modifying ext repo
- fix: corrected copy paste errors
- fix(vector): move vector tests from ext/riscv-tests/ submodule to tests/
- fix(build): fix Gem path for bundler & ignore generated test/dump files
rebase vector branch to latest
merge rebase
Pushing a first cut to move to WSL+devbranch workflow.
In vec.idl: Added log2_sew field to enable using shifts (with correct amounts :-) Renamed log2_multiplier to log2_lmul and fixed fractional LMUL values In vset*.yaml: Read the content of xs1 (not the register number) as the value of AVL Read the content of xs2 (for vsetvl) as the value of new VTYPE In rv32-vector.yaml: Fixed name from old copy-paste; added "V extension" to description
Used concatenation to write back results. TBD: Replace with bitfield write when it's released in IDL. TBD: Remove hard coding length of Vector registers which is a work-around for a bug in using rv-vector config to build the ISS (and since rv32 config doesn't and shouldn't define VLEN parameter.
Created 4 files for params and removed the params property from V.yaml
Fixed constexpr errors and got rv32 config to build.
…ined()
Fixed the workaround for the case of a compared value not being included for
a parameter in a config, viz., 64 for SV{39,48,57}X4_TRANSLATION for rv32.
- Added vsetvli_rs1_eq_zero test to verify that vl is set to vlmax when rs1 is x0 for cases of SEW=8,32,64 and LMUL=8. - Also renamed the old vsetvli test to vsetvli_vl_lt_vlmax to reflect the intent better.
Tested Henrik's new directory structure under tests/isa/. Added new tests for vsetvli. Started adopting naming convention of <instr>_<coverage_cond> for vsetvli.
Collaborator
|
To make this review clearer and easier you may want to rebase vector branch onto main |
Collaborator
Actually, the issue is that the vector branch has #891 in it, so it's ahead of main. That should resolve itself when 891 merges |
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