Remove ACLE submodule

This involves moving from the ACLE intrinsic definitions (which aren't
available for SVE at this point) to a JSON file. This was derived from
ARM's documentation[^1], and then relicensed under `MIT OR Apache-2.0` for
use in this repository.

[^1]: https://developer.arm.com/architectures/instruction-sets/intrinsics

.gitmodules

@@ -1,3 +0,0 @@
-[submodule "crates/intrinsic-test/acle"]
-	path = crates/intrinsic-test/acle
-	url = https://github.com/ARM-software/acle.git

ci/docker/aarch64-unknown-linux-gnu/Dockerfile

@@ -10,7 +10,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   qemu-user \
   make \
   file \
-  clang-13 \
+  clang-15 \
   lld
 
 ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \

ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile

@@ -10,7 +10,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   qemu-user \
   make \
   file \
-  clang-13 \
+  clang-15 \
   lld
 ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \
     CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -L /usr/arm-linux-gnueabihf" \

ci/run.sh

@@ -137,10 +137,10 @@ esac
 
 if [ "${TARGET}" = "aarch64-unknown-linux-gnu" ]; then
     export CPPFLAGS="-fuse-ld=lld -I/usr/aarch64-linux-gnu/include/ -I/usr/aarch64-linux-gnu/include/c++/9/aarch64-linux-gnu/"
-    RUST_LOG=warn cargo run ${INTRINSIC_TEST} --release --bin intrinsic-test -- crates/intrinsic-test/acle/tools/intrinsic_db/advsimd.csv --runner "${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}" --cppcompiler "clang++-13" --skip crates/intrinsic-test/missing_aarch64.txt
+    RUST_LOG=warn cargo run ${INTRINSIC_TEST} --release --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json --runner "${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}" --cppcompiler "clang++-15" --skip crates/intrinsic-test/missing_aarch64.txt
 elif [ "${TARGET}" = "armv7-unknown-linux-gnueabihf" ]; then
     export CPPFLAGS="-fuse-ld=lld -I/usr/arm-linux-gnueabihf/include/ -I/usr/arm-linux-gnueabihf/include/c++/9/arm-linux-gnueabihf/"
-    RUST_LOG=warn cargo run ${INTRINSIC_TEST} --release --bin intrinsic-test -- crates/intrinsic-test/acle/tools/intrinsic_db/advsimd.csv --runner "${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}" --cppcompiler "clang++-13" --skip crates/intrinsic-test/missing_arm.txt --a32
+    RUST_LOG=warn cargo run ${INTRINSIC_TEST} --release --bin intrinsic-test -- intrinsics_data/arm_intrinsics.json --runner "${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}" --cppcompiler "clang++-15" --skip crates/intrinsic-test/missing_arm.txt --a32
 fi
 
 if [ "$NORUN" != "1" ] && [ "$NOSTD" != 1 ]; then

crates/intrinsic-test/Cargo.toml

@@ -1,13 +1,16 @@
 [package]
 name = "intrinsic-test"
 version = "0.1.0"
-authors = ["Jamie Cunliffe <[email protected]>"]
-edition = "2021"
+authors = ["Jamie Cunliffe <[email protected]>",
+    "James McGregor <[email protected]",
+    "Adam Gemmell <[email protected]"]
 license = "MIT OR Apache-2.0"
+edition = "2021"
 
 [dependencies]
 lazy_static = "1.4.0"
 serde = { version = "1", features = ["derive"] }
+serde_json = "1.0"
 csv = "1.1"
 clap = "2.33.3"
 regex = "1.4.2"

crates/intrinsic-test/missing_aarch64.txt

@@ -23,39 +23,6 @@ vusdotq_lane_s32
 vusdotq_s32
 vusdot_s32
 
-# Implemented in Clang but missing from CSV
-vcmla_f64
-vcmla_lane_f64
-vcmla_laneq_f64
-vcmlaq_lane_f64
-vcmlaq_laneq_f64
-vcmlaq_rot180_lane_f64
-vcmlaq_rot180_laneq_f64
-vcmlaq_rot270_lane_f64
-vcmlaq_rot270_laneq_f64
-vcmlaq_rot90_lane_f64
-vcmlaq_rot90_laneq_f64
-vcmla_rot180_f64
-vcmla_rot180_lane_f64
-vcmla_rot180_laneq_f64
-vcmla_rot270_f64
-vcmla_rot270_lane_f64
-vcmla_rot270_laneq_f64
-vcmla_rot90_f64
-vcmla_rot90_lane_f64
-vcmla_rot90_laneq_f64
-
-# Implemented in Clang and stdarch but missing from CSV
-vmov_n_p64
-vmovq_n_p64
-vreinterpret_f32_p64
-vreinterpret_p64_s64
-vreinterpretq_f32_p128
-vreinterpretq_f32_p64
-vreinterpretq_p128_p64
-vreinterpretq_p64_p128
-vtst_p16
-vtstq_p16
 
 # Missing from both Clang and stdarch
 vrnd32x_f64
@@ -67,30 +34,17 @@ vrnd64xq_f64
 vrnd64z_f64
 vrnd64zq_f64
 
-# QEMU 6.0 doesn't support these instructions
-vmmlaq_s32
-vmmlaq_u32
-vsm3partw1q_u32
-vsm3partw2q_u32
-vsm3ss1q_u32
-vsm3tt1aq_u32
-vsm3tt1bq_u32
-vsm3tt2aq_u32
-vsm3tt2bq_u32
-vsm4ekeyq_u32
-vsm4eq_u32
-vusmmlaq_s32
-
 # LLVM select error in debug builds
-vqshlu_n_s16
-vqshlu_n_s32
-vqshlu_n_s64
-vqshlu_n_s8
-vqshlub_n_s8
-vqshlud_n_s64
-vqshluh_n_s16
-vqshluq_n_s16
-vqshluq_n_s32
-vqshluq_n_s64
-vqshluq_n_s8
-vqshlus_n_s32
+#vqshlu_n_s16
+#vqshlu_n_s32
+#vqshlu_n_s64
+#vqshlu_n_s8
+#vqshlub_n_s8
+#vqshlud_n_s64
+#vqshluh_n_s16
+#vqshluq_n_s16
+#vqshluq_n_s32
+#vqshluq_n_s64
+#vqshluq_n_s8
+#vqshlus_n_s32
+

crates/intrinsic-test/missing_arm.txt

@@ -23,15 +23,6 @@ vusdotq_lane_s32
 vusdotq_s32
 vusdot_s32
 
-# Implemented in Clang and stdarch but missing from CSV
-vtst_p16
-vtstq_p16
-
-# QEMU 6.0 doesn't support these instructions
-vmmlaq_s32
-vmmlaq_u32
-vusmmlaq_s32
-
 # Implemented in Clang and stdarch for A64 only even though CSV claims A32 support
 __crc32d
 __crc32cd
@@ -214,110 +205,29 @@ vrndx_f32
 vrndxq_f32
 
 # LLVM select error in debug builds
-vqrshrn_n_s16
-vqrshrn_n_s32
-vqrshrn_n_s64
-vqrshrn_n_u16
-vqrshrn_n_u32
-vqrshrn_n_u64
-vqrshrun_n_s16
-vqrshrun_n_s32
-vqrshrun_n_s64
-vqshrn_n_s16
-vqshrn_n_s32
-vqshrn_n_s64
-vqshrn_n_u16
-vqshrn_n_u32
-vqshrn_n_u64
-vqshrun_n_s16
-vqshrun_n_s32
-vqshrun_n_s64
-vrshrn_n_s16
-vrshrn_n_s32
-vrshrn_n_s64
-vrshrn_n_u16
-vrshrn_n_u32
-vrshrn_n_u64
-vshrq_n_u64
-vshr_n_u64
-
-# Failing tests: stdarch has incorrect results compared to Clang
-vqshlu_n_s16
-vqshlu_n_s32
-vqshlu_n_s64
-vqshlu_n_s8
-vqshluq_n_s16
-vqshluq_n_s32
-vqshluq_n_s64
-vqshluq_n_s8
-vsli_n_p16
-vsli_n_p8
-vsli_n_s16
-vsli_n_s32
-vsli_n_s64
-vsli_n_s8
-vsli_n_u16
-vsli_n_u32
-vsli_n_u64
-vsli_n_u8
-vsliq_n_p16
-vsliq_n_p8
-vsliq_n_s16
-vsliq_n_s32
-vsliq_n_s64
-vsliq_n_s8
-vsliq_n_u16
-vsliq_n_u32
-vsliq_n_u64
-vsliq_n_u8
-vsri_n_p16
-vsri_n_p8
-vsri_n_s16
-vsri_n_s32
-vsri_n_s64
-vsri_n_s8
-vsri_n_u16
-vsri_n_u32
-vsri_n_u64
-vsri_n_u8
-vsriq_n_p16
-vsriq_n_p8
-vsriq_n_s16
-vsriq_n_s32
-vsriq_n_s64
-vsriq_n_s8
-vsriq_n_u16
-vsriq_n_u32
-vsriq_n_u64
-vsriq_n_u8
-
-# These produce a different result on Clang depending on the optimization level.
-# This is definitely a bug in LLVM.
-vadd_f32
-vaddq_f32
-vcvt_s32_f32
-vcvt_u32_f32
-vcvtq_s32_f32
-vcvtq_u32_f32
-vfma_f32
-vfma_n_f32
-vfmaq_f32
-vfmaq_n_f32
-vfms_f32
-vfmsq_f32
-vmla_f32
-vmla_lane_f32
-vmla_n_f32
-vmlaq_f32
-vmlaq_lane_f32
-vmlaq_n_f32
-vmls_f32
-vmls_lane_f32
-vmls_n_f32
-vmlsq_f32
-vmlsq_lane_f32
-vmlsq_n_f32
-vmul_lane_f32
-vmul_n_f32
-vmulq_lane_f32
-vmulq_n_f32
+#vqrshrn_n_s16
+#vqrshrn_n_s32
+#vqrshrn_n_s64
+#vqrshrn_n_u16
+#vqrshrn_n_u32
+#vqrshrn_n_u64
+#vqrshrun_n_s16
+#vqrshrun_n_s32
+#vqrshrun_n_s64
+#vqshrn_n_s16
+#vqshrn_n_s32
+#vqshrn_n_s64
+#vqshrn_n_u16
+#vqshrn_n_u32
+#vqshrn_n_u64
+#vqshrun_n_s16
+#vqshrun_n_s32
+#vqshrun_n_s64
+#vrshrn_n_s16
+#vrshrn_n_s32
+#vrshrn_n_s64
+#vrshrn_n_u16
+#vrshrn_n_u32
+#vrshrn_n_u64
+#vshrq_n_u64
+#vshr_n_u64